Memory Design Considerations That Affect Price and Performance

1. Memory Design Considerations That Affect Price and Performance Bill Gervasi Technology Analyst, Transmeta Chairman, JEDEC Memory Parametrics bilge@transmeta.com

2. Posed at the Last Conference Why will DDR-I at 400 MHz data rate be a “boutique” solution? Why will DDR-II at 400 MHz data rate be a “mainstream” solution?

3. Agenda • JEDEC/Industry Roadmap • Factors for Market Acceptance • Difficulties in Achieving 400 MHz • Factors Affecting Cost • Wild Cards – What Can Change?

4. RAM Evolution 5400MB/s DDR667 4300MB/s MainstreamMemories DDR533 3200MB/s “DDR II” DDR400 2700MB/s Simple,incrementalsteps DDR333 2100MB/s “DDR I” DDR266

5. Factors for Market Acceptance • Industry Focus • Number of Competing Suppliers • JEDEC standard • Laws of Physics

6. Industry Focus • The JEDEC roadmap represents the industry focus for mainstream products • DDR-I tops out at 333 MHz data rate • DDR-II starts at 400 MHz data rate • This DOES NOT mean that DDR-I at 400 MHz data rate will not ship in volume • It DOES mean that there will be price premiums for this speed bin

7. What do I mean by “Focus”? • There is serious work to hit 400 MHz • Vendor interoperable solutions • Mix and match module configurations • Signal integrity analysis • We are counting picoseconds • No JEDEC standard yet proposed for DDR-I at 400 MHz data rate

8. For Example… How we are getting more refined in timing analysis with DDR-II… The Charge Transfer Model for input timing measurement and derating

9. DDR-I Input Timing Model CLOCK CLOCK Setup Hold INPUT Timing derating by input signal slew rate: 1.0V/ns = base value 0.5V/ns = base value + 50ps 0.4V/ns = base value + 100ps This got us through DDR333… The Old Way

10. However… This simplified model was good enough for DDR333 data rates, but leaves picoseconds of available timing lying around needed for 400+!!! DDR266 Data Setup/Hold = 750 ps DDR333 Data Setup/Hold = 600 ps DDR400 Data Setup/Hold = 400 ps DDR533 Data Setup/Hold = 350 ps Can’t waste time!!!

11. “Focus” on Input Timing DDR-II Charge Transfer Timing Model • All inputs have a slew rate dependent aspect tEXT and an independent aspect tINT • Summing tEXT + tINT gives input transition time tT • Transition time tT has min and max values • Differential input transitions inherently different The New Way INPUT tEXT tINT tT

12. tEXT for Slow Slew Rate, Single Ended AT = Charge to Transition VIHAC = VSAT VIHDC VREF tEXT tINT VILDC VILAC=VSAT

13. tEXT for Fast Slew Rate, Single Ended VSAT = Saturation Voltage AT = ASAT + AADD VIHAC =VSAT ASAT = Charge to Saturation VIHDC AADD = Charge after Saturation VREF tSAT VILDC tEXT tINT VILAC =VSAT

14. tEXT for Slow Slew Rate, Differential AT = Charge to Transition VIHAC =VSAT VIHDC VREF VILDC VILAC =VSAT tINT tEXT

15. tEXT for Fast Slew Rate, Differential AT = ASAT + AADD VIHAC =VSAT VIHDC VREF VILDC VILAC =VSAT tEXT tINT

16. “Focus” on Timing CLOCK tTmin DDR-II Charge Transfer Timing Model Setup = tTmax of input - tTmin of reference CLOCK Setup tTmax INPUT

17. “Focus” on Timing CLOCK tTmax DDR-II Charge Transfer Timing Model Hold = tTmax of reference - tTmin of input CLOCK Hold tTmin INPUT

18. How does this help…? The Charge Transfer Model gives a higher accuracy for setup and hold relationships It also provides a way to accurately describe derating for input slew rate These models are negotiated with all suppliers to define an industry standard

19. DDR-II Input Derating Tables Clock (mV/ps avg) Strobe (mV/ps avg) SETUP SETUP 0.5 1.0 2.0 0.5 1.0 2.0 + + + + + + 0.5 0.5 Data (mV/ps) Addr (mV/ps) ¾ + ¾ + 0 0 1.0 1.0 ¾ ¾ ¾ ¾ ¾ ¾ 2.0 2.0 Strobe (mV/ps avg) Clock (mV/ps avg) HOLD HOLD 0.5 1.0 2.0 0.5 1.0 2.0 + + + + + + 0.5 0.5 Addr (mV/ps) + 0 ¾ + 0 ¾ Data (mV/ps) 1.0 1.0 ¾ ¾ ¾ ¾ ¾ ¾ 2.0 2.0

20. Derating Using Charge Transfer • Accuracy from derating both signals and references • Result is a two dimensional matrix relating inputs & their references • Identified inherent asymmetries in derating of setup & hold when mixing single ended with differential signals • Memory module mixes impact slew rates • The Charge Transfer model controls system cost by enabling more complex timing analysis

21. Charge Transfer on DDR-I? • This model would also help design high speed DDR-I systems • However, the work to retrofit this to DDR-I needs to be done to benefit from it

22. DDR-II Improvements DDR-II introduces technical improvements that reduce the cost of achieving high speeds • Prefetch 4 • Differential data strobe • I/O Calibration • Lower I/O Voltage • On-Die Termination

23. Prefetch 4

24. Moving to the Next Level • Today’s SDRAM architectures assume an inexpensive DRAM core timing • DDR I (DDR200, DDR266, and DDR333) prefetches 2 data bits: increase performance without increasing timing costs • DDR II (DDR400, DDR533, DDR667) prefetches 4 bits internally, but keeps DDR double pumped I/O

25. Prefetch 2 Versus 4 CK READ data Core access time Prefetch 2 Prefetch 4 Costs $$$ Column cycle time Essentially free Costs $$$

26. Prefetch Impact on Cost By doubling the prefetch depth, cycle time for column reads & writes relaxed, improving DRAM yields DDR Family Pre-fetch Data Rate Cycle Time Starts to get REAL EXPENSIVE! 2 266 7.5 ns DDR-I 2 333 6 ns Comparable to DDR266 in cost 2 400 5 ns 4 400 10 ns DDR-II 4 533 7.5 ns 4 667 6 ns

27. Why Not Prefetch = 8? • DIMM width = 64 bits • PCs use 64b, servers use 128b (2 DIMMs) • 64 byte prefetch okay for PC, but… • 128 byte prefetch for servers wastes bandwidth • DDR-II must service all applications well to insure maximum volume  minimum cost

28. Differential Data Strobe

29. Differential Data Strobe • Just as DDR added differential clock to SDR • DDR II adds differential data strobe to DDR I • Transition at the crosspoint of DQS and DQS

30. Differential Data Strobe VREF DQS DQShigh time DQSlow time Normal balanced signal VREF DQS DQShigh time DQSlow time Mismatched Rise & Fall signal Error!

31. Differential Data Strobe DQS VREF DQS DQShigh time DQSlow time Normal balanced signal DQS VREF DQS DQShigh time DQSlow time Mismatched Rise & Fall signal Significantly reduced symmetry error

32. I/O Calibration

33. I/O Calibration • Balance pull-up and pull-down driver strength • Reduces timing errors from signal asymmetry • Insures signal rise and fall times are similar Data DRAM Controller Data Reference

34. 1.8V I/O Voltage

35. 1.8V Signaling 2.5V VDDQ 1.8V 1.60V VDDQ VIHac 1.43V 1.15V VIHdc 1.25V VIHac VREF 1.03V VILdc VIHdc 1.07V 0.90V VREF VILac VILdc 0.77V 0.90V VILac 0.65V VSS VSS 0V SSTL_2 SSTL_18

36. I/O Voltage Impact on Timing • Assume 1mV/ps edge slew rate • DDR-I = 700 mV (VILVIH) = 700 ps • DDR-II = 500 mV (VILVIH) = 500 ps • Helps meet the need for speed • Signal integrity is a serious challenge at DDR-I and 400 MHz data rate

37. On-Die Termination

38. On-Die Termination VTT =VDDQ ¸ 2 Data Reduces system cost while improving signal integrity Controller DDR-I DRAM Data Controller DDR-II DRAM VDDQ ¸ 2 VDDQ ¸ 2

39. What Can Change?

40. Wild Cards • 100% yield of 5 ns cycle time cores (magic?) • Industry gets excited about engineering DDR-I at 400 MHz • DDR-II slow transition from schedule or price • Feature creep • Die penalties • DRAM guys trying to make money for once

41. Conclusions • DDR-I at 400 will ship in volume but • …not likely to cross over $/bit • Industry focus is on transition to DDR-II for 400+ MHz data rates

42. Thank You