An Architecture-Level Leakage Simulator

1. An Architecture-Level Leakage Simulator Yuh-Fang Tsai Embedded & Mobile Computing Design Center Dept of Computer Science & Engineering Penn State University 12.4.2003

2. Outline • Motivation • Power Simulator Framework • Device Model/Process Parameters • Hierarchical Modeling & Validation • Device-Level Modeling • Circuit-Level Modeling • Architecture-Level Modeling • Results • Summary • Future Work

3. Motivation • Leakage power increases with technology scaling. • Temperature and process variation impacts on leakage power. • Need of architecture-level leakage power estimation tool considering temperature feedback and process variations. • Need of leakage simulator with ability to differentiate subthreshold and gate leakage. From B. Doyle. From A. Keshavarzi.

4. Power Simulator Framework • Enhancing Trimaran tool set to include energy model. Layout Abstraction Power Simulator Leakage Power =f (temp, process) Cache Simulator HotSpot Thermal Parameters Dynamic Power VLIW Simulator Power Breakdown Temperature Profile

5. Layout Abstraction Power Simulator Cache Simulator HotSpot Thermal Parameters VLIW Simulator Power Breakdown Temperature Profile Power Simulator Framework • Dynamic energy read from a table. • HSPICE simulation to get energy of the integer/floating point functional units, caches, TLBs, the pipeline control latches, the IO unit, and the register files. • Clock power estimated by [1]*. • Activity based. Leakage Power =f (temp, process) Dynamic Power *[1] Duarte, D, et al, “A Clock Power Model to Evaluate Impacts of Architectural and Technology Optimizations.”, ITVLSI, Vol. 10, No. 6, Dec. 2002

6. Layout Abstraction Power Simulator Cache Simulator HotSpot Thermal Parameters VLIW Simulator Power Breakdown Temperature Profile Power Simulator Framework • Leakage energy estimated by analytical models which take temperature and process variations as parameters. • Consumed every cycle. Leakage Power =f (temp, process) Dynamic Power

7. Layout Abstraction Power Simulator Cache Simulator HotSpot Thermal Parameters VLIW Simulator Power Breakdown Temperature Profile Power Simulator Framework • HotSpot [2]* is integrated for dynamic temperature feedback every 10K cycles. • Layout similar to Intel Itanium. • Initial temperature: 60oC. Leakage Power =f (temp, process) Dynamic Power *[2] Hot-Spot, LAVA research group, University of Virginia, http://www.lava.cs.virginia.edu/HotSpot

8. Device Model and Process Parameters • Based on 65nm BPTM and MIT Well-tempered bulk-Si device. • Tune Tox, Nch to match Intel fabrication data: Ion=570µA/µm (NMOS) & 285µA/µm (PMOS) Ioff=~100nA/µm

9. Hierarchical Modeling Get total subthreshold and gate leakage of a processor from circuit-level model considering architecture configurations. Get subthreshold leakage and gate leakage of each transistor Analyze each basic component of circuit block to get the total subthreshold and gate leakage of each circuit block.

10. Device-Level Modeling-Subthreshold Leakage K: fitting parameter from Hspice simulation & Standard deviation With process variations Relationship between parameter.

11. Device-Level Modeling-Gate Leakage With process variations

12. Device-Level Validation • Compare model estimates with Hspice results. • Average Error: 1.56% and 12% for temperature and process variations, respectively.

13. Device-Level Modeling Problem • The fitting parameters which relate the process variation parameters to the subthreshold leakage are not consistent for single variation parameter and simultaneous variation of multiple parameters. • In the experiment set-up, the parameters for simultaneous variation of multiple parameters are used to simulate the real case.

14. Circuit-Level Modeling • SiO2 is assumed to be the gate oxide material and gate leakage of PMOS is negligible. • Leakage components for circuits.

15. Circuit-Level Modeling • Analyze basic component of regular structures—the major source of leakage. • Assume SRAM precharged to High. • Assume all input combinations have equal probability. • Estimate leakage of irregular structures by the equivalent transistor width. Isubp 1 0 Igaten3

16. Circuit-Level Modeling

17. Circuit-Level Validation • Compare model estimates with Hspice simulation results. • Average error: 5.31%

18. Architecture-Level Modeling • Memory Components • Clock Network & & where

19. Architecture-Level Modeling • Pipeline Control Latches • Arithmetic and Control Logic • Assume half of transistors of a circuit block is on/off. (Weqn=1/2*Weqn_total & Weqp=1/2* Weqp_total) • Assume stack effect reduces subthreshold leakage power by 20% and gate leakage by 40%. (Fs=20% & Fg=40%)

20. Architecture-Level Validation • Compare model estimates with Hspice simulation results. • Average error: 6.53%

21. Results-Power Breakdown

22. Results-Temperature Effect Result of benchmark: 132.ijpeg

23. Results- Effect of Process Variations With process variations Pleak / Ptotal = 50.08W / 74.91W Without process variations Pleak / Ptotal = 20.96W / 45.79W 66% 46% Variations: L: 12.5%, Tox: 10%, and Vth: 5%. Result of benchmark Atomcatv.

24. Isub and Igate Breakdown

25. Summary • An architecture-level leakage power simulator considering dynamic temperature feedback and process variations is built. • Observations: • Leakage power will exceed 50% of chip power budget for next generation technology. • Without using leakage reduction techniques, caches consume the majority of leakage power. • Using high-Vth cells in cache and considering temperature profiling, leakage power of processor units with higher activity becomes no less important. • Leakage power increases by 20%~30% in architecture level when accounting for nominal process variations.

26. Future Works • Fix the model for simultaneous multiple variation of process parameters. • Include the power supply variation in the model and integrated the power supply level feedback tool.

27. THANK YOU