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Chapter 9 Bootloader

Chapter 9 Bootloader. Learning Objectives. Need for a bootloader. What happens during a reset. Boot modes and processes. Memory map. What is the bootloader?. VCC. VCC. When the DSP is NOT powered or under reset the internal program memory is in a random state. Boot Config. Addr. 0000.

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Chapter 9 Bootloader

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  1. Chapter 9 Bootloader

  2. Learning Objectives • Need for a bootloader. • What happens during a reset. • Boot modes and processes. • Memory map.

  3. What is the bootloader? VCC VCC • When the DSP is NOT powered or under reset the internal program memory is in a random state. Boot Config Addr 0000 EMIF L2 Cache L1P Cache 0001 0002 0003 ... CPU EPROM DMA L1D Cache C6211/C6711

  4. What is the bootloader? VCC VCC • When the DSP is powered and the CPU is taken out of reset the internal memory is still in a random state and the program will start running for address zero. Boot Config Addr 0000 0000 EMIF L2 Cache L1P Cache 0001 0001 0002 0002 0003 0003 ... CPU EPROM DMA PC=0000 PC=0001 PC=0002 PC=0003 L1D Cache C6211/C6711

  5. What is the bootloader? VCC VCC • With the boot, a portion of code can be automatically copied from external to internal memory. Boot Config EMIF L2 Cache L1P Cache CPU EPROM DMA L1D Cache C6211/C6711

  6. What happens at reset: System timeline • When the device is held in reset: • The device is initialised to the default state. • Most 3-state outputs are in the high impedance state. /RS pin CPU Reset Device Reset

  7. What happens at reset: System timeline • On the rising edge of the /RS pin: • The processor checks the boot mode configuration (HD[4:3]) and starts the boot loader. • The EDMA automatically copies 1K bytes from the beginning of CE1 location to the internal program memory starting at address zero. /RS pin CPU Reset Device Reset CPU Reset Boot load in operation

  8. What happens at reset: System timeline • Once the boot loader has finished initialising the internal memory the CPU is taken out of reset. • The CPU starts running from address zero. /RS pin CPU Reset Device Reset CPU Reset Boot load in operation

  9. ‘C6211 and ‘C6711 Memory map • The ‘C6211 and ‘C6711 has only one memory map, MAP0. • Internal memory is always located at address zero. • Internal memory can be used as either program or data.

  10. ‘C6211 and ‘C6711 Memory map

  11. Boot modes and processes • Two questions need to be answered about the bootloader, these are: • What methods of boot are available and how are they selected? • How does the DSP know what type of memory it is going to boot from?

  12. Bootloader operational modes • The TMS320C6211 and ‘C6711 support the following boot configurations: (1) Host Port Interface (HPI) boot. (2) 8-bit ROM boot. (3) 16-bit ROM boot. (4) 32-bit ROM boot. Note: with the ‘C6211 and ‘C6711 there is no “no-boot” mode as for the other ‘C6000 processors.

  13. Bootloader configuration HD[4:3] Boot mode 00 01 10 11 HPI boot 8-bit ROM boot 16-bit ROM boot 32-bit ROM boot • The boot mode is selected by pulling the HD[4:3] pins (HPI data bus pins) high or low at reset. • Depending on the voltages on this pins one of the four modes is selected.

  14. Endianess configuration HD[8] Device operation 0 1 Big endian Little endian • The endian mode is determined at the same time as boot mode. • Pulling pin HD[8] high or low selects the following endian modes. Note: ensure that the software development tools are also configured with the same endian type as the hardware.

  15. Clock mode configuration CLKMODE0 PLL frequency multiplier 0 1 No multiplication Input frequency is multiplied by 4 • The input clock mode is also determined at the same time as boot mode. • Pulling CLKMODE0 pin high or low selects the following modes.

  16. Boot process: HPI boot mode 17 DSPINT HPIC • In this mode the following sequence is used: • The CPU is held in reset while the remaining of the device is released. • The host processor initialises the CPU’s memory space through the HPI. • When all the necessary memory is initialised the host processor takes the CPU out of reset by writing a ‘1’ to the DSPINT bit filed of the Host Port Interface Control (HPIC) register.

  17. Boot process: HPI boot mode /RS Boot Config L2 Cache L1P Cache HPI HOST CPU DMA EMIF DRAM L1D Cache C6211/C6711

  18. Boot process: HPI boot mode • Question: How does the host processor check that the memory has been initialised correctly? • Answer: The host can read and write to any address so it can check by reading the ‘initialised’ memory.

  19. Boot process: HPI boot mode • Question: If an external memory needs to be initialised via the HPI how do you ensure that the EMIF is set correctly? • Answer: The first thing the Host should do is to write the EMIF register then write to the external memory locations.

  20. Boot process: ROM boot mode • In this mode the following sequence is used: • The CPU is held in reset while the bootloader operates. • The bootloader copies 1Kbytes from CE1 with the default settings to internal memory at address zero. • CPU is taken out of reset. • CPU starts running code from address zero.

  21. Boot process: ROM boot mode VCC /RS Boot Config L2 Cache L1P Cache EMIF ROM CPU DMA DRAM L1D Cache C6211/C6711

  22. Chapter 9 Bootloader - End -

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