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Low-voltage techniques

Low-voltage techniques. Mohammad Sharifkhani. Reading. Text Book I, Chapter 4 Text Book II, Section 11.7. Power, Energy, Speed. Speed Energy  Battery lifetime Instantaneous power  Package, cooling. If leakage is ignored, P x Tpd is equal to E; independent of Vth and Speed:

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Low-voltage techniques

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  1. Low-voltage techniques Mohammad Sharifkhani

  2. Reading • Text Book I, Chapter 4 • Text Book II, Section 11.7

  3. Power, Energy, Speed • Speed • Energy  Battery lifetime • Instantaneous power  Package, cooling If leakage is ignored, P x Tpd is equal to E; independent of Vth and Speed: work at the slowest speed; lowest VDD to minimize E (and P).

  4. Efficient design approaches

  5. Power, Energy, Speed • Both Energy and Speed are important: • Energy x Delay is the right index (?) • To minimize power • Lower VDD (quadratic dependence, +both leakage and dynamic power) • Reduce C • Lower pt • Lower VDD  Delay  4 possibilities • Dual Vth (low Vth only for critical path) • Multiple VDD (low VDD for non critical path) • Parallel, pipeline arch. • Lower Vth to recover the speed

  6. VDD scaling

  7. VDD scaling

  8. VDD scaling

  9. VDD scaling vs. delay

  10. Processing options

  11. Architecture Trade-off for Fixed-rate ProcessingReference Datapath

  12. Parallel data path

  13. Pipeline data path

  14. Comparison

  15. Multiple supply issues Still on!  DC current

  16. Block level voltage scaling

  17. Block level multiple supply voltage

  18. Multiple VDDs

  19. Optimum V2/V1 is around 0.7V Hamada, CICC’01

  20. Multiple supply voltages • Two supply voltages per block are optimal • Optimal ratio between the supply voltages is 0.7 • Level conversion is performed on the voltage boundary, using a level-converting flip-flop (LCFF) • An option is to use an asynchronous (combinatorial) level converter • More sensitive to coupling and supply noise

  21. Level converting FF

  22. Shimazaki, ISSCC’03

  23. VDDH drives

  24. Inverse discrete cosine

  25. Delay sensitivity

  26. VDD temporal variation • Design for Dynamically Varying VDD • • Ring oscillator. • • static logic • • Dynamic logic (& tri-state busses). • • Sense amp (& memory cell). • Max. allowed |dVDD/dt| → Min. CDD = 100nF (0.6μm) • Circuits continue to properly operate as VDD changes VDD t

  27. Static CMOS

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