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Chapter 6

IEG4020 Telecommunication Switching and Network Systems. Chapter 6. Switch Design Principles for Broadband S ervices. Fig. 6.1. (a) Multicasting by separate point-to-point connections from source to destinations; (b) multicasting using multicast switches in network. B. C. B. C.

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Chapter 6

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  1. IEG4020 Telecommunication Switching and Network Systems Chapter 6 Switch Design Principles for Broadband Services

  2. Fig. 6.1. (a) Multicasting by separate point-to-point connections from source to destinations; (b) multicasting using multicast switches in network. B C B C High access bandwidth D D A E A E Network Multicast Packet Switch (a) (b)

  3. Fig. 6.2. An input-output tree generated by generalized self-routing algorithm. 0000 0000 0001 0001 0010 0010 0011 0011 0100 0100 1001 0101 0101 1010 1111 0110 0110 0111 0111 1000 1000 1001 1001 1010 1010 1011 1011 1100 1100 1101 1101 1110 1110 1111 1111 1 0 1001 1001 1001 1010 1001 1001 0 1 1 0 1010 1010 1010 1010 1111 1111 1 1 1 1111 1111 1111

  4. Fig. 6.3. A multicast packet switch that consists of a copy network and a point-to-point switch. Copy Network Point- to-point Switch

  5. Fig. 6.4. The Boolean interval splitting algorithm generates the equivalent input-output tree of a packet with interval addresses. 0000 0000 0001 0001 0010 0010 0011 0011 0100 0100 0101 0101 0110 0110 0111 0111 1000 1000 1001 1001 1010 1010 1011 1011 1100 1100 1101 1101 1110 1110 1111 1111 0101 0101 0101 0101 1 0111 0111 0101 0101 0101 0 1010 0101 0101 1 0110 0110 0110 0101 0110 0111 0111 1 0111 0 0110 0 0110 0111 0111 1000 1 1 1001 1000 1000 0111 1010 1010 1010 0 1000 1000 0 1000 1000 1001 0 1001 1001 1000 1010 1010 1 1001 1 1001 1010 1010 0 1010 1010

  6. 000 CN=2 001 000 010 001 CN=3 100 010 101 CN=1 101 111 Boolean Interval Splitting Algorithm • Output interval : (MIN, MAX) • Copy number : CN = MAX- MIN + 1 • MIN(k-1) = m1 … mn MAX(k-1) = M1 … Mn At stage k, • if mk = Mk = 0 or mk = Mk = 1, send packet out on link 0 or link 1. • If mk = 0 , Mk = 1, duplicate packet & modify header (a) for packet on link 0, MIN(k) = MIN(k-1) = m1 … mn MAX(k) = M1 … Mk-1011…1 (b) for packet on link 1, MIN(k) = M1 … Mk-1100…0 MAX(k) = MAX(k-1)=M1 … Mn

  7. Nonblocking Condition of Broadcast Banyan Network • A copy network is nonblocking if it can produce the packet copies requested if the total number of copies does not exceed N. • A broadcast banyan network is nonblocking if active inputs x1 … xm and their sets of outputs Y1 .. Ym satisfy • Y1 < … < Ym or Y1 > … > Ym where Yi< Yj means all address in Yi < all addresses in Yj • Active inputs are concentrated.

  8. Fig. 6.5. The structure of a nonblocking copy network. Three active packets, A, B, and C, and their copy numbers Copy-number running sums Address intervals Copy indices of packets concentrated Outputs 0 A:0 0 0 A:1 1 A:(0,1) 2 B:0 2 A: 2 2 C:0 3 B:(2,2) 3 C:1 4 B: 1 C:(3,6) 7 C:2 5 C: 4 7 C:3 Packets order unchanged 6 7 7 Running Adder Network Dummy Address Encoder Reverse Banyan Network Broadcast Banyan Network Trunk Number Translator BCN CN BCN IR MIN, MAX BCN CI TN

  9. Nonblocking Copy Network BCN : Broadcast Channel Number CN : Copy Number IR : Index Reference CI : Copy Index TN : Trunk Number CI= output address - IR

  10. Fig. 6.6. An adder in the running-adder network of the copy network: adding both the running sums of the activity bits and the copy numbers. 0 0 0 + + + 0 0 Address assigned = Sum of all activity bits above = Running sum - 1 + + + 0 + + + 0 + + + + + + + + + + + + + + + Running Sum of copy numbers Running Sum of activity bits Info A c a Packet A + Info B c+d a+b Info B d b Packet B Packet B

  11. e.g. CN 1 N Copy Network Performance Improvement • How to remove bias against higher input ports? • How to perform partial service of a copy request ?

  12. Fig. 6.7. Illustration showing the principle for achieving input fairness by shifting the service priority order and the principle of achieving efficiency by call-splitting in a copy network. CN Packet E : 2 Packet A : 2 Packet B : 1 Packet C : 3 Packet D : 1 Copy Network Packet E : 2 (New starting point) Packet C : 2 Packet D : 1 Copy Network Current time slot Next time slot

  13. Fig. 6.8. The architecture and operation of a cyclic running-adder network. Starting indicator Running sum of activity bits Running sum of copy numbers a b c d e f g 0 1 1 0 2 2 0 4 3 1 7 5 5 + + + 0 2 1 0 3 2 0 4 3 1 9 6 6 + + + 0 4 1 0 6 2 0 8 4 1 3 7 7 + + + 1 2 1 1 2 1 1 2 1 1 2 1 0 + + + 1 3 2 1 3 2 1 3 2 0 1 1 1 + + + 0 3 2 1 5 3 1 5 3 0 2 1 2 + + + 0 2 1 1 5 3 1 5 3 0 0 0 3 + + + 0 1 1 0 1 1 0 4 3 1 6 4 4 + + + a d e f g b c RSA SIA RSA RAA RSA SIC RSC RAC Packet A + RSA SIB RSB RAB Packet B If SIB=0 SIC=SIA If SIB=1 SIC=SIB RSC=RSA+RSBRAC=RAA+RAB RSC=RSBRAC=RAB

  14. Update of starting Indicator, SI • SI remains the same until overflow occurs. 1if RSN-1 N 0otherwise 1ifRSi-1 N andRSi> N 0otherwise { SI0= { SIi=

  15. Update of SCN. ( Served copy number ) SCN0=RS0 min (N, RSi) – RSi-1if RSi-1< N 0otherwise { SCNi=

  16. Fig. 6.9. Cyclically monotone routing address gives rise to packet collisions in reversed banyan network. The packets at ports 2 and 6 are inactive. (Note: inputs connected to outputs of the cyclic running-adder network in Fig. 6.8.) Running sum of activity bit minus one Packet collision occurs 0 4* 0 1 5* 1 2 2 3 3 0 4 1 4 5 2 5 6 6 7 7 3

  17. Running Address Computed Served Copy Number Served Copy Number Copy Number 1 1 0 1 2 1 1 1 0 2 2 2 2 1 1 1 3 2 2 2 4 1 0 1 1 5 Cyclic Running-adder Network Running-adder Network + Dummy Address Encoder Reverse-banyan Network Broadcast Banyan Network (a)

  18. 4* Routing Address Computed 5* Served Copy Number Copy Number 1 4* 2 2 5* 1 0 2 2 0 1 Reverse-banyan Network 1 1 1 2 2 1 0 1 3 0 Cyclic Running-adder Network + Dummy Address Encoder 1 Broadcast Banyan Network 2 3 (b)

  19. Fig. 6.10. Three different approaches to concentrate active packets. The starting-point packet is marked by encircling its copy number, routing address in the reverse-banyan network, and served copy number. Routing Address Computed Served Copy Number Copy Number 1 4* 4* 2 2 5* 5* 1 0 2 2 0 0 1 1 1 1 1 2 2 2 1 0 1 3 3 Cyclic Running-adder Network + Dummy Address Encoder Dilated Reverse-banyan Network Broadcast Banyan Network (c)

  20. Fig. 6.11. General replication scheme using interval splitting. Output Address Intervals 0000 0000 0000 0001 0001 Packet A 0001 0010 0010 0011 0011 0000 0100 0100 0101 0101 0101 Packet B 0110 0110 0111 0111 1000 1000 1001 1001 1010 1010 1011 1011 1100 1100 1101 1101 1110 1110 1111 1111 0000 0000 0000 0001 0001 0000 0000 0001 0011 0011 0010 0010 0000 0011 0010 0101 0011 0100 0100 0100 0011 0100 0101 0101 0100 0100 0101 0101 0101 0101 Headers of Copies of Packet B and the use of Routing Bits

  21. Fig. 6.12. A deadlock example with a deterministic routing policy: set switch elements into bar state under “don’t care” situations. A packet fails to be duplicated regardless of the number of stages while the bottom link is idle at each stage. F=2 0000 F=1 0001 F=1 0010 F=1 0011 0100 F=1 0101 F=1 F=1 0110 0111 F=1 1000 F=1 1001 F=1 F=1 1010 1011 F=1 F=1 1100 F=1 1101 F=1 1110 1111 Idle input

  22. Fig. 6.13. Packet replication in a Manhattan-street network using interval splitting: an example in which the source node is (1,1) and the packet requests six copies. 0,0 0,1 0,2 0,3 1,0 1,1 1,2 1,3 2,0 2,1 2,2 2,3 3,0 3,1 3,2 3,3

  23. Concept of Path Switching • Traffic signal at cross-roads • Use predetermined conflict-free states in cyclic manner • The duration of each state in a cycle is determined by traffic loading • Distributed control N Traffic loading: NS: 2 EW:  W E NS traffic EW traffic S Cycle

  24. k x k n x m m x n k x k n x m m x n n x m k x k m x n Background Why Clos networks? • Modularity – Switch size can be enlarged by adding modules. • Resources sharing –Middle stage routing resources can be shared by all inputs.

  25. Fig. 6.14. A Three-stage Clos network. Input stage Middle stage Output stage 0 0 k x k n x m m x n 1 1 n-1 n-1 0 0 0 n n k x k n x m m x n n+1 n+1 2n-1 2n-1 1 1 1 n(k-1) n(k-1) k x k n x m m x n n(k-1)+1 n(k-1)+1 nk-1 nk-1 k-1 k-1 m-1 k input modules m central modules k output modules

  26. Fig. 6.15 Routing in Clos network. 0 0 0 1 1 1 2 2 3 2 Properties of Clos Network • Any central module can only assign to one input of each input module, and one output of each output module. • Input i and output j can be connected through any central module. • The number of alternate paths between input i and output j is equal to the number of central module.

  27. Background Routing schemes in Clos network • Static routing, e.g. circuit switching • Peak rate is reserved for each call, • Low utilization under multimedia environment. • Dynamic routing, packet switching • Routing pattern is rearranged in every time slot according to arriving packets • High complexity of routing computation.

  28. Utilization Dynamic Packet Switching ? Static Circuit Switching Slot-by-slot Route Computation Complexity Motivations

  29. Virtual Path in Clos Network time slot 0 Virtual Path(Capacity) 0 0 0 0 0 1 1 1 2 2 1 1 2 eij – number of cells that can be routed from input moduleito output module j in a frame of two time slots. time slot 1 0 0 0 1 1 2 2 1 2 2 2 Middle-stage routing pattern in a Clos network (Frame size f=2) Regular bipartite graph representation Edge matrix and constraints

  30. Bipartite Graph time slot 0 0 0 0 0 0 input module = left node 1 1 1 output module = right node 2 2 1 1 2 time slot 1 0 0 Central module = color (complete matching) 0 1 1 2 2 1 2 2 2 Middle-stage routing pattern in a Clos network (Frame size f=2) Regular bipartite graph representation

  31. Fig. 6.16. Correspondence between the middle-stage route scheduling in a Clos network and the edge coloring of the bipartite multigraph. (a) Three-stage Clos network. (b) The equivalent regular bipartite graph. Input Modules Output Modules 3 x 3 4 x 4 3 x 3 0 0 0 0 0 1 1 1 1 1 2 2 2 2 3 3 3 2 3 (b) (a) Central Module 1 Central Module 2 Central Module 3

  32. Switch Parameters Ii: Input module i Oj: Input module j ij : the number of cells per time slot from Iito Oj eij(t) : the number of edges from Iito Oj of the corresponding bipartite graph in time slot t. Cij: the number of virtual path between Ii and Oj

  33. Cell Switching Circuit Switching • The capacity Cij of the virtual path between Ii and Oj must satisfy • If the routing of circuit switched Clos network is fixed, the connection pattern will be the same in every time slot. So, What is in between?

  34. Quasi-static path switching Routing in Clos Network • If m > n, for any given traffic matrix ij, such that • There exists a finite integer f and a sequence of integer matrices [eij(t)], t=1,2,..,f such that

  35. Circuit Switching Cell Switching Path Switching Routing Static f=1 Dynamic f   Quasi-static f > 1 Connection pattern Constant in every time slot Varying in every time slot Changes periodically Given traffic matrix[ij], Routing Schemes in Clos Network

  36. Capacity Matrix [Cij] Traffic Matrix [ij] Integer Edge Matrix [eij] Capacity allocation Round off Regular bipartite graph Periodic routing pattern Edge-colored bipartite graph Time-space interleaving Edge coloring Procedureof Scheduling

  37. Scheduling of Path Switching 1.0 0 0 0.3 0.4 0.7 1 1 1.4 0.7 0.5 0.3 2 2 1.0 0 1 time slot 0,2,… Capacity Assignment & Route Assignment 2 0 1 time slot 1,3,… Virtual Path Traffic loading matrix 2 Resulting middle-stage routing pattern

  38. Capacity Allocation 1.0 1.4 0 0 0 0 Optimization e.g. minimize mean packet delay based on M.D/1 model subject to capacity constraints 0.3 0.4 0.5 0.6 0.7 1.1 1 1 1 1 1.4 1.8 0.7 1.0 0.5 0.3 0.7 0.6 2 2 2 2 1.0 1.3 Traffic loading matrix (per slot) Capacity matrix (per slot)

  39. Round-off Procedure FRAME SIZE f Transform capacity per slot into capacity per frame with 1/f Round-off error R.M.S. Error=0.416 Capacity matrix (per slot) R.M.S. Error=0.133 Round to an integer matrix Edge matrix (per frame)

  40. Edge-Coloring of Bipartite Graph 0 0 0 0 Edge-coloring Methods Hungarian algorithm Sequence searching, O(N2) Suitable for irregular graphs Parallel algorithm for regular bipartite graph G.F.Lev, O(Nlog23N), 1982 T.T.Lee, O(Nlog22N), 1996 for N=2n 1 1 1 1 2 2 2 2 Edge-coloring Edge-color bipartite graph Edge matrix

  41. Time-Space Interleaving time slot 0 COLOR {0, 1, .., fm-1} {0, 1,…, m-1}x{0, 1, …, f-1} SPACExTIME c=s x f + t 0 0 0 1 1 1 2 time slot 1 0 (fm=6) COLOR (m=3) SPACE (f=2) TIME 2 2 Orange 0 0 0 1 Green 1 1 0 Blue 2 2 0 Edge-colored bipartite graph Pink 3 0 1 Cyan 4 1 1 Grey 5 2 1 2 Resulting middle-stage routing pattern Time-Space Interleaving = Decomposition of doubly stochastic matrix

  42. Input Modules Output Modules 0 0 a r t 0 0 1 1 2 2 3 3 0 0 4 4 5 5 2 1 0 3 3 0 0 4 2 1 1 4 4 5 5 1 1 1 0 2 2 3 1 1 5 4 4 5 4 5 2 2 2 2 2 3 3 1 1 0 0

  43. Fig. 6.15. Illustration of time-space interleaving principle. 0 0 0 1 1 0 0 0 1 1 2 2 2 2 0 0 0 2 2 Slot 0 0 0 1 1 1 1 1 1 2 2 2 1 2 1 0 0 2 2 1 1 1 0 0 2 2 2 0 0 0 1 1 0 0 0 2 1 1 2 2 2 1 1 0 2 2 Slot 1 0 0 1 1 0 0 1 1 2 2 2 1 2 0 0 2 1 1 2 1 1 0 0 2 2 2

  44. TABLE I LATIN SQUARE ASSIGNMENT O0 O1 O2 … Ok-1 I0 A0 A1 A2 … Ak-1 I1 Ak-1 A0 A1 … Ak-2 . . . . . . . . . . . . . . . . . . Ik-1 A1 A2 A3 … A0

  45. TABLE II ROUTE ASSIGNMENT BY LATIN SQUARE FOR UNIFORM TRAFFIC Color O0 O1 Color a= r·f + t 0 1 2 3 4 5 + I0 0,1,2 3,4,5 Central Module r = a/f 0 0 1 1 2 2 I1 3,4,5 0,1,2 Time slot t = a mod f 0 1 0 1 0 1 Latin square : edge-coloring Transformation from color assignment into time space pair Central module assignment Central Module O0 O1 Central Module O0 O1 I0 0,1 2 I0 0 1,2 I1 2 0,1 I1 1,2 0 time slot 0 time slot 1

  46. Fig. 6.16. Routing scheduling in the middle stage for uniform traffic. (a) connection pairs in central modules. (b) time slot 0. (c) Time slot 1. Connected I/O pairs at Time Slot Central Module 0 1 0 I0/O0, I1/O1(BAR) I0/O0, I1/O1(BAR) 1 I0/O0, I1/O1(BAR) I0/O1, I1/O0(CROSS) 2 I0/O1, I1/O0(CROSS) I0/O1, I1/O0(CROSS) (a) 0 0 0 0 0 0 1 1 1 1 1 1 2 2 (b) (c)

  47. Fig. 6.17. Routing scheduling in central modules for the second example of uniform traffic.(a) Time slot 0.(b) Time slot 1. (c) Time slot 2. 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 2 1 2 2 1 2 2 1 2 3 3 3 3 3 3 2 2 2 4 4 4 4 4 4 5 5 3 5 5 5 5 3 3 (c) (a) (b)

  48. Fig. 6.18 Virtual path between input module i and module j. Input Buffers Outputs Buffers 0 0 1 Virtual Path 1 Aggregate Arrival Rate ij Capacity Cij n-2 n-2 n-1 n-1 Input Module i Output Module j

  49. 3x4 0 4x3 0 0 3x4 1 4x3 1 1 3x4 2 4x3 2 2 3 (a)

  50. 3x4 0 4x3 0 0 3x4 1 4x3 1 1 3x4 2 4x3 2 2 3 (b)

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