1 / 32

CS61C Finishing the Datapath: Subtract, Multiple, Divide Lecture 21

CS61C Finishing the Datapath: Subtract, Multiple, Divide Lecture 21. April 14, 1999 Dave Patterson (http.cs.berkeley.edu/~patterson) www-inst.eecs.berkeley.edu/~cs61c/schedule.html. Outline. Review Datapath, ALU Including subtract in a 32-bit ALU Review Binary Multiplication

ryanmartinez
Download Presentation

CS61C Finishing the Datapath: Subtract, Multiple, Divide Lecture 21

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CS61C Finishing the Datapath: Subtract, Multiple, Divide Lecture 21 April 14, 1999 Dave Patterson (http.cs.berkeley.edu/~patterson) www-inst.eecs.berkeley.edu/~cs61c/schedule.html

  2. Outline • Review Datapath, ALU • Including subtract in a 32-bit ALU • Review Binary Multiplication • Administrivia, “What’s this Stuff Good For” • Multiplier • Review Binary Division • Divider • Conclusion

  3. Review 1/5: Steps in Executing MIPS Subset 1) Fetch Instruction and Increment PC 2) Read 1 or 2 Registers 3) Mem-ref: Calculate Address Arith-log: Perform Operation Branch: Compare if operands == 4) Load: Read Data from Memory Store: Write Data to Memory Arith-og: Write Result to Register Branch: if operands ==, Change PC 5) Load: Write Data to Register

  4. Data Out Address Data In Data Out Address Data In Data Out Registers PC Instruction Cache Data Cache ALU Step 1 Step 2 Step 3 (Step 4) Review 2/5 : A Datapath for MIPS (Step 4,5)

  5. Review 3/5: Hardware Building Blocks OR Gate AND Gate Symbol Definition Symbol Definition A A C C B B Inverter Multiplexor Definition Definition Symbol Symbol D A C A 0 C B 1

  6. A 0 B 1 C + 2 Review 4/5: Add 1-bit Adder to 1-bit ALU CarryIn Op • Now connect 32 1-bit ALUs together Definition CarryOut

  7. A0 A1 0 0 B0 B1 1 1 C1 C0 + + 2 2 A31 0 B31 1 C31 + 2 CarryIn Op Review 5/5: 32-bit ALU • Connect CarryOuti to CarryIni+1 • Connect 32 1-bit ALUs together • Connect Op to all 32 bits of ALU ... • Does 32-bit And, Or, Add • What about subtract?

  8. 2’s comp. shortcut: Negation (Lecture 7) • Invert every 0 to 1 and every 1 to 0, then add 1 to the result • Sum of number and its inverted rep. (“one’s complement”) must be 111...111two • 111...111two= -1ten • Let x mean the inverted representation of x • Then x + x = -1  x + x + 1 = 0  x + 1 = -x • Example: -4 to +4 to -4x : 1111 1111 1111 1111 1111 1111 1111 1100twox : 0000 0000 0000 0000 0000 0000 0000 0011two+1: 0000 0000 0000 0000 0000 0000 0000 0100two() : 1111 1111 1111 1111 1111 1111 1111 1011two+1: 1111 1111 1111 1111 1111 1111 1111 1100two

  9. How Do Subtract? • Suppose added input to 1-bit ALU that gave the one’s complement of B • What happens if set CarryIn0 to 1 in 32-bit ALU? • 32-bit Sum = A + B + 1 • Then if select one’s complement of B (B), Sum isA + B + 1 = A + (B + 1) = A + (-B) = A - B • If modify 1-bit ALU, can do Subtract as well as And, Or, Add

  10. 0 1 1-bit ALU with Subtract Support CarryIn Binvert Op A 0 1 B C + 2 Definition CarryOut

  11. A0 A1 0 0 1 1 C0 C1 B0 B1 + + 2 2 0 0 0 1 1 1 CarryIn Binvert Op 32-bit ALU • 32-bit ALU made from AND gates, OR gates, Inverters, Multiplexors • Performs 32-bit AND, OR,Add,Sub (2’s complement) • Op, Binvert, CarryIn are control lines; control datapath ... ... A31 0 1 C31 B31 + 2

  12. MULTIPLY: From Lecture 9 • Paper and pencil example: Multiplicand 1000Multiplier 1001 1000 0000 0000 1000 Product 01001000 • m bits x n bits = m+n bit product • MIPS: mul, mulu puts product in pair of new registers hi, lo; copy by mfhi, mflo • 32-bit integer result in lo

  13. MULTIPLY • Binary multiplication is easy: • 0  place 0 ( 0 x multiplicand) • 1  place a copy ( 1 x multiplicand) • Shift the multiplicand left before adding to product • 3 versions of multiply hardware & algorithm: • Successive refinement to get to real version • Go into first version in detail, give idea of others

  14. Shift-add multiplier (version 1) 1000 1001 1000 0000 0000 1000 01001000 64-bit Multiplicand reg, 64-bit ALU, 64-bit Product reg, 32-bit Multiplier reg Shift Left Multiplicand 64 bits Shift Right Multiplier 64-bit ALU 32 bits Write Product Control 64 bits Multiplier = datapath + control

  15. 1. Test Multiplier0 Shift-Add Multiply Algorithm V. 1 Multiplier0 = 0 Multiplier0 = 1 ProductM’plierM’cand 0000 0000 0011 0000 00100000 0010 0001 0000 01000000 0110 0000 0000 10000000 0110 0000 0001 0000 0000 0110 1a. Add multiplicand to product & place the result in Product register 2. Shift the M’cand register left 1 bit 3. Shift the M’plier register right 1 bit 31nd repetition? No: < 32 repetitions Yes: 32 repetitions Done

  16. Administrivia • Project 5: Due today • Next Readings: 3.12, 4.9 • Optional: Appendix D “An Alternative to RISC: the Intel 80x86,” Computer Architecture, A Quantitative Approach, 2/e • Optional: RISC Survey (including HP ISA) ftp://mkp.com/COD2e/Web_Extensions/survey.htm • 9th homework: Due Friday (Ex. 7.35, 4.24) • 10th homework: Due Wednesday 4/21 7PM • Exercises 4.43, 3.17 (assume each instruction takes 1 clock cycle, performance = no. instructions executed * clock cycle time, ignore CPI comment)

  17. Administrivia: Rest of 61C F 4/16 Intel x86, HP instruction sets; 3.12, 4.9 W 4/21 Performance; Reading sections 2.1-2.5F 4/23 Review: Procedures, Variable Args(Due: x86/HP ISA lab, homework 10) W 4/28 Processor Pipelining; section 6.1F 4/30 Review: Caches/TLB/VM; section 7.5(Due: Project 6-sprintf in MIPS, homework 11) M 5/3 Deadline to correct your grade record W 5/5 Review: Interrupts/PollingF 5/7 61C Summary / Your Cal heritage Sun 5/9 Final Review starting 2PM (1 Pimintel) W 5/12 Final (5PM 1 Pimintel); mds@cory

  18. “What’s This Stuff Good For?” Aquanex system Swimmers looking for an edge over the competition can now use tiny half-ounce sensors that give them instant feedback on their power and their stroke rate, length and velocity, shown as real-time performance graphs generated by the PC. Unlike most, this swimmer generates more arm power in his butterfly than in his freestyle. "If he learns to apply that strength to his freestyle, he'll almost certainly decrease his time."One Digital Day, 1998 www.intel.com/onedigitalday Will computers help us utilize untapped physical potential as well as intellectual potential?

  19. Observations on Shift-Add Multiply V.1 • 1/2 bits in multiplicand always 0=> 64-bit adder is wasted • 0’s inserted in left of multiplicand as shifted=> least significant bits of product never changed once formed • Instead of shifting multiplicand to left, shift product to right?

  20. Shift-add Multiplier Version 2 (v. slide 14) • 32-bit Multiplicand reg, 32-bit ALU, 64-bit Product reg, 32-bit Multiplier reg Multiplicand 32 bits Shift Right Multiplier 32-bit ALU 32 bits Write Product Control 64 bits Shift Right Multiplier = datapath + control

  21. Shift-Add Multiplier Version 3 • Product reg. wastes space that exactly matches size of Multiplier reg combine Multiplier reg and Product reg “0-bit” Multiplier reg Multiplicand 32 bits 32-bit ALU 0 bits Write Product (M’plier) Control Shift Right 64 bits Multiplier = datapath + control

  22. Divide: From Lecture 9 1001Quotient Divisor 10001001010 Dividend–1000 10 101 1010 –1000 10 Remainder (or Modulo result) Dividend = Quotient x Divisor + Remainder • See how big a number can be subtracted, creating quotient bit on each step • Binary  1 * divisor or 0 * divisor

  23. DIVIDE HARDWARE Version 1 1001 1000 1001010 –1000 10 101 1010 –1000 10 64-bit Divisor reg, 64-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg Shift Right Divisor 64 bits Shift Left Quotient 64-bit ALU 32 bits Write Remainder Control 64 bits • Put Dividend into Remainder to start, collect Quotient 1 bit at a time

  24. n+1 repetition? Done Divide Algorithm V. 1 Start: Place Dividend in Remainder 1. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register. Remainder < 0 Remainder ≥ 0 Test Remainder 2a. Shift the Quotient register to the left setting the new rightmost bit to 1 2b. Restore the original value by adding the Divisor register to the Remainder register, and place the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0 3. Shift the Divisor register right1 bit No: < n+1 repetitions Yes: n+1 repetitions (n = 4 here)

  25. Example Divide Algorithm V. 1 • Takes n+1 steps for n-bit Quotient & Rem. Remainder Quotient Divisor (-Divisor)0000 0111 0000 0010 0000 (1110 0000)1 1110 01112b00003 0000 01110001 0000 (1111 0000) 1 1111 01112b00003 0000 01110000 1000 (1111 1000) 1 1111 11112b00003 0000 01110000 0100 (1111 1100)

  26. Example Divide Algorithm V. 1 (cont’d) Remainder Quotient Divisor (-Divisor)0000 0111 0000 0000 0100 (1111 1100)1 0000 00112a00013 0000 0011 0000 0010 (1111 1110) 1 0000 00012a00113 0000 0001 0000 0001 (1111 1111) • Original division of 0111two (7) by 0010two (2) gives a quotient of 0011two (3) plus a remainder of 0001two (1)

  27. Observations on Divide Version 1 • 1/2 bits in divisor always 0=> 1/2 of 64-bit adder is wasted => 1/2 of divisor is wasted • Instead of shifting Divisor to right, shift Remainder to left?

  28. Quotient DIVIDE HARDWARE Version 2 (v. slide 28) • 32-bit Divisor reg, 32-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg Divisor 32 bits Shift Left 32-bit ALU Write Remainder Control Shift Left 64 bits

  29. DIVIDE HARDWARE Version 3 • Eliminate Quotient register by combining with Remainder as shifted left 32-bit “0-bit” Quotient reg Divisor 32 bits 32-bitALU 0-bits Write Remainder (Quot.) Control Shift Left 64 bits

  30. Multiply, Divide Algorithms Explain MIPS Multiplicand/Divisor • mul puts product in pair of regs hi, lo; • 32-bit integer result in lo • MIPS: div, divu puts Remainer into hi, puts Quotient into lo 32 bits 32-bitALU Hi Lo Write Product/ Remainder Product/ Quotient Control Shift 64 bits

  31. PC Registers Instruction Cache Data Cache ALU Step 1 Step 2 (Step 4) A Revised Datapath for MIPS (Step 4, 5) Step 3 X, / Hi, Lo registers Steps 3-19

  32. “And in Conclusion..” 1/1 • Subtract included to ALU by adding one’s complement of B • Multiple by shift and add • Divide by shift and subtract, then restore by add if didn’t fit • Can Multiply, Divide simply by adding 64-bit shift register to ALU • MIPS allows multiply, divide in parallel with ALU operations • Next: Intel and HP Instruction Set Architectures

More Related