CSE430/830 Course Project Tutorial

1. CSE430/830 Course Project Tutorial Instructor: Dr. Hong Jiang TA: Dongyuan Zhan Project Duration: 01/26/11 – 04/29/11

2. Objectives • Get familiar with the fundamental ideas of computer architecture • Finish a semester-long project: building a pipelined 32-bit RISC processor with • HW-based data hazard resolution mechanisms • a static branch predictor • instruction/data caches • assembler & bubble-sort application • Practice efficient teamwork that makes your work splendid. CSE430/830 Course Project Tutorial

3. Teams • Since there are exactly 30 students, each team is required to have 3 (or 4) members • A team would better have a member who has taken CSE230 and its Lab • Each team is required to have a team leader who coordinates the group’s project events • Each team needs to maintain a project wiki to update the group’s progress CSE430/830 Course Project Tutorial

4. Tasks • Task 1: determine the ISA • tailor the ISA that is targeted at the bubble-sort application • write the bubble-sort program and compile it with your own designed assembler • Task 2: pipeline the processor • add pipeline stage registers • add HW-based data hazard resolution mechanisms • Task 3: add a static branch predictor • move the branch decision and branch address calculation to the “instruction decode” stage • “always-not-taken ” is the easiest • performance counters are required to monitor the prediction accuracy CSE430/830 Course Project Tutorial

5. Tasks • Task 1: determine the ISA • tailor the ISA that is targeted at the bubble-sort application • write the bubble-sort program and compile it with your own designed assembler • Task 2: pipeline the processor • add pipeline stage registers • add HW-based data hazard resolution mechanisms • Task 3: add a static branch predictor • move the branch decision and branch address calculation to the “instruction decode” stage • “always-not-taken ” is the easiest • performance counters are required to monitor the prediction accuracy CSE430/830 Course Project Tutorial

6. Tasks • Task 4: incorporate instruction/data caches • both are directly mapped • #(sets), block size, write policy are critical design parameters • performance counters are required to monitor the hit rates of the caches • Project Wiki • a log of weekly meeting • the high-level/architectural view of your design • the verification of the correctness & efficiency of individual components and the entire system • a summary of the work that you have done and that lags behind CSE430/830 Course Project Tutorial

7. Expected Demonstration Results CSE430/830 Course Project Tutorial

8. Milestones • Milestone 1: team formed —Jan. 28, 2011 • Milestone 2: Task 1 finished — Feb. 23, 2011 • Milestone 3: Task 2 finished — Mar. 16, 2011 • Milestone 4: Task 3 finished — Mar. 30, 2011 • Milestone 5: Task 4 finished — Apr. 20, 2011 • Milestone 6: project designs & report submitted —Apr. 27, 2011 • Milestone 7: project demonstration — Apr. 28 - 29, 2001 CSE430/830 Course Project Tutorial

9. Grading Criteria • completeness and correctness of the implementation • 60 points for all of the 4 specific tasks • well-designed and informative project wiki • 15 points • project demonstration • 5 points • project report • 20 points CSE430/830 Course Project Tutorial

10. Tools • Hardware • Altera DE-2 board with a Cyclone-II FPGA • Software • Quartus-II Web Edition 10.1 • synthesize your FPGA design • USB Blaster Driver • enable DE-2 to communicate with Quartus-II. • USB-to-Serial Driver • Virtualize a USB port as a RS232 port • Putty • a free implementation of Telnet, SSH and Hyperterminal CSE430/830 Course Project Tutorial

11. USB Blaster Port Altera DE-2 Development Board Power Button RS232 FPGA 50MHz Clock Generator LCD Panel Slide Switches Press Buttons CSE430/830 Course Project Tutorial

12. Software • How to use Quartus-II IDE • very detailed tutorials are in “$PATH\Project Documents\DE2_System_v1.6\DE2_tutorials\” • some important memos: • open an existing project by double clicking a “*.qpf” file • specify the FPGA when creating a project • Cyclone-II EP2C35F672C6 • connect the inputs and outputs of your design to FPGA’s pins in Quartus-IIAssignmentPins • download an “*.sof” file to DE2 via Quartus-IIToolsProgrammer CSE430/830 Course Project Tutorial

13. Software • differentiate functional and timing simulations in Quartus-IIAssigmentSettingsSimulation SettingsSimulation Mode • How to utilize the USB-to-Serial communication • Prerequisites • install Putty & the USB-to-Serial driver • download “uart_example.sof” to DE2 • Steps • connect DE2 to a laptop with a USB-to-Serial cable • in “Device ManagerPort(COM & LPT)”, check out the COM number, which may change when you connect to a different USB port on your laptop CSE430/830 Course Project Tutorial

14. Software CSE430/830 Course Project Tutorial

15. Software specify the “flow control” to be “None” click “Open” check the “serial” box specify the “serial line” with the COM # specify the “Speed” to be 115200 CSE430/830 Course Project Tutorial

16. Software The Hyperterminal used to demonstrate the uart-to-usb communication content CSE430/830 Course Project Tutorial

17. Suggestions for a Good Project Carry out efficient teamwork Plan well and make steady progress Keep project wiki well-organized Use version control system, such as SVN, to manage your source code Deploy effective and efficient debugging strategy Be active in discussing with the TA CSE430/830 Course Project Tutorial

18. Resources • IDE • http://adsl.unl.edu/quartus.exe • Project Documents • containing almost everything you need for the project • http://adsl.unl.edu/proj_docs.zip • Project Discussion Board • http://groups.google.com/group/unl-cse430-2011s • Altera Documents & Forum • http://www.altera.com/literature/lit-index.html • http://www.alteraforum.com/ CSE430/830 Course Project Tutorial