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Reference HW1, write VHDL models and a simple test bench for following problem. Use type Std_Logic for all signals; All reset should be asynchronous. Then run simulation on ModelSim and compare the waveforms. 1. Model the schematic shown:.
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Reference HW1, write VHDL models and a simple test bench for following problem. Use type Std_Logic for all signals; All reset should be asynchronous. Then run simulation on ModelSim and compare the waveforms. 1. Model the schematic shown: Fall 2003 - EE5319/EE4328 Homework 2-1 (all homeworks don’t request to turn in) P "and" D1 Q1 Q2 Clk Rst B. Show waveforms for Q1, Q2, D1, P and Rst by hand first. Assume Rst is same width of one clock period. Clk Q1 Q2 D1 P Rst .
Y Fall 2003 - EE5319/EE4328 Homework 2-2 (all homeworks don’t request to turn in) • 2. Write a VHDL model for the following schematic (use type Std_Logic for all signals). Could you write more than one VHDL coding styles (there are more than one way to express the logic)? A D "nor" B "nand" E "or" C • 3. Using CSA (Concurrent Signal Assignment) to write a VHDL model for the following schematic (use type Std_Logic for all signals). D(0) D(1) X D(2) D(3) Sel(0) Sel(1) .
