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Green Computing

Green Computing. Reducing the environmental and economic impact of energy consumption by low-power Integrated Circuit Design Faculty Forum, April 1, 2008. Peiyi Zhao, Ph.D. Department of Mathematics, Computer Science, and Physics Chapman University. Overview. Integrated Circuits

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Green Computing

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  1. Green Computing Reducing the environmental and economic impact of energy consumption by low-power Integrated Circuit Design Faculty Forum, April 1, 2008 Peiyi Zhao, Ph.D. Department of Mathematics, Computer Science, and Physics Chapman University

  2. Overview • Integrated Circuits • Power Consumption • Green Computing • Understanding the levels of a Computer • Where does the power go? • How can we reduce power?

  3. Integrated Circuits • The first transistor was built in 1947. • The first integrated circuit was invented in 1959. • Market driven by military, computer, communications, and consumer needs. • Equipment once used by the military are now available on a number of consumer products.

  4. Integrated Circuits are Everywhere Climate Control Lighting Dashboard Display Door Modules Engine Control Fuel Injection Entertainment Chassis Electronics Safety Control

  5. Integrated Circuit Market • Six billion microcontroller units were shipped in 2004, predicted to be increasing by 10% each year from 2004-2009 (Instate Inc. market research) • Semiconductor annual revenue of 2004 is estimated at US $211.4 billion.

  6. Power Consumption • Desktop consumption has reached 100 watts • Total Personal Computer(400 million) energy usage in 2000 = 26 nuclear power plants • Power is the bottleneck of improving the system performance • Power consumption is causing serious problems because of excessive heat. Water Cooled Computer (www.water-cooling.com)

  7. Nuclear Reactor Pentium 4 Hot Plate Pentium 3 Pentium 2 Pentium Pro Pentium 486 386 Power Consumption of Processor

  8. Power Consumption • As circuit speed increases, power consumption grows • Designing low power circuits has been the most important issue • Mobile applications demand long battery life • Low power consumption is listed as the second greatest challenge for the industry

  9. The Current Situation • Energy provisioning is arguably the most important business, geo-political, and societal issue of our time • Global Warming is influencing policies and laws which require energy usage and greenhouse emissions to be measured and controlled • The cost of energy and increases in IT power requirements present significant expense, supply, and handling challenges for data centers • “Intelligent Energy” Dr. Bernard S. Meyerson, IBM Fellow, VP Strategic Alliances and CTO, IBM Systems & Technology Group, on ASE – Great Energy Efficiency Day, February 14, 2007 - Washington, DC

  10. Power Consumption & Data Centers Internet • Where are the web pages you browse? • Data Center • One single room in Datacenter contains 100 Racks • 1 Rack = 5 to 20 kW • Contributed to the 2000/2001 California Energy Crisis Client Racks Data Center • “Intelligent Energy” Dr. Bernard S. Meyerson, IBM Fellow, VP Strategic Alliances and CTO, IBM Systems & Technology Group, on ASE – Great Energy Efficiency Day, February 14, 2007 - Washington, DC Gateway

  11. 200 M tons of CO2= CO2 produced by 40 million cars

  12. Atmospheric CO2 concentrations measured at Mauna Loa Observatory.

  13. Cooling the Data Center Flickr.com • Current coolants: CFCs and HCFCs = Ozone Depletion • The other alternative coolant: HFC = increase in green house emission 1300 times (http://www.cs.virginia.edu/kim/courses/cs771/lectures/CS771-22.ppt) • Moving Datacenters to exotic locations(Microsoft -> Cold Siberia, Sun -> underground) Siberia umw.edu Underground Japan

  14. Energy Usage of Data Centers http://www.westportnow.com • 2006: $15 Billion for energy usage • Impact of 10% Reduction of Power Consumption of Data Centers • $15b x 10% = $1.5 billion in savings • 200 x 10% = 20 million tons of CO2 • 4 million cars(Number of cars that would have to be taken off the road to reduce the same amount of CO2 emissions.)

  15. Reducing Power Consumption • Data centers = huge energy bill + produce CO2 + green house emission + air pollution… • Moore’s Law: transistor density doubles every 18 months. • “We must reduce power usage. Computing is part of the solution, part of the problem”-- ”Sustainable Computing,” David Douglas, VP, Ecological Responsibility, Sun Microsystems Source: University of Delaware

  16. Green Computing • In order to achieve sustainable computing, we need to rethink from a “Green Computing” perspective. • GreenComputing: • Maximize energy efficiency • Reduce of the use of hazardous materials such as lead • Maximize recyclability of both a defunct product and of any factory waste. • “Green Computing” in view of energy efficiency at the nanometer scale - design low power consumption integrated circuits at 180nm and below.

  17. A Perfect “Green Computing” Example • A super low-power “processor”: • 800x faster • 1000x more memory • 3000x less power

  18. A super low power “Processor”

  19. What can we do about power? • Understand all levels of the computer • Understand where power is dissipated • Think about ways to reduce power usage at all levels

  20. The 6 Levels of a Computer 5 High Level Programming 4 Assembly Language Software 3 Operating System 2 Instruction Set Architecture 1 Digital Logic Hardware 0 Integrated Circuit

  21. The Need for Both Sides “The performance of software systems is dramatically affected by how well software designers understand the basic hardware technologies at work in a system. Similarly, hardware designers must understand the far-reaching effects their design decisions have on software applications.” - John Hennessy, President of Stanford University & David Patterson, UC Berkeley, President of ACM “[Students] should know the device, layout, circuit, architecture, algorithm, and system-6 levels.” - Dr. Mehdi Hatamian, V.P, Broadcom, Nov.2006

  22. The Chapman Approach 5 High Level Programming CPSC 230/231, 350, 353, 354, 402, 408 4 Assembly Language CPSC 250 3 Operating System CPSC 380 2 Instruction Set Architecture CPSC 252 1 Digital Logic CPSC 330 0 Integrated Circuit CPSC 465

  23. Where does power go? Power Breakdown of an Itanium 2 Processor

  24. Processor Clock • Power consumption is proportional to clock frequency. • Clock frequency: how often the clock changes every second; of course, every change of the clock consumes power. • Analogous to how many times the motor spins per second in your car. • Traditionally only one edge of the clock is used to process information, and the other edge is ignored.

  25. Using Double Edge Clocking • Using double edge clocking, the clock frequency can be reduced to half. • “Low Power clock branch sharing Double-EdgeFlip-Flop,” P. Zhao, Jason McNeely, Pradeep Golconda, agdy A. Bayoumi, Kuang W.D, and Robert Barcenas, IEEE Transactions on Very Large Scale Integration (VLSI) Systems,Vol.15, No.3, pp. 338-345, March 2007. • Proposed clock branch sharing technique: used least number of clocked transistors to implement double edge clocking efficiently. Conventional Single edge Design: Proposed Design:

  26. Potential Savings 33% x 0.5 = 15% Savings from Double Edge Usage by using half of the frequency Clock Power Usage Power Savings $15b x 15% = $2.25b Annual Energy Cost of Data Centers Savings Annual Savings

  27. Peer Reviewed Journal Publications, Patent for Low Power Consumption Peer Reviewed Journal Publications (all as first author) • P. Zhao, T. Darwish, M. Bayoumi, “High Performance and Low Power Conditional Discharge Flip-Flop,” in Institute of Electrical and Electronics Engineers (IEEE) Transactions on Very Large Scale Integration (VLSI) Systems, Vol 12., No. 5, pp. 477-484, May 2004. • P. Zhao, Jason McNeely, Pradeep Golconda, Magdy A. Bayoumi, Kuang W.D, and Robert Barcenas, “Low Power Clock Branch Sharing Double-Edge Triggered Flip-Flop,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems,Vol.15, No.3, pp. 338-345, March 2007. • Journal Paper under Revision: P. Zhao, Jason McNeely, G. P. Kumar, Nan Wang, M. Bayoumi, and Robert Barcenas, “Low Power Clocked-pseudo-NMOS Flip-flops for Level Conversion in Dual Supply Systems,” submitted to IEEE Transactions on Very Large Scale Integration (VLSI) Systems under 1st revision. Patent • Single transistor clocked flip flop, by P.Zhao, T.Darwish, M.Bayoumi

  28. Student Research Assistance • Chapman undergraduate student Robert Barcenas is involved with research and is one of the co-authors of a journal paper • Two previous students who worked with me on my project were hired by Intel

  29. Low Power Research Recognition • Our research results are comparable to the results from other more well-funded research groups: • Our designs outperformed those of Intel and UC Davis • Our designs have attracted industry attention from Toshiba

  30. Thank You

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