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ASC, a SystemC extension for modeling Asynchronous Systems, and its application to an Asynchronous NoC

Outline. Asynchronous NoC and SystemCAsynchronous SystemC (ASC)Asynchronous NoC modelingConclusion. Context and Motivations. Network On ChipHigh throughput, low power, scalability, modularity, QoS.Asynchronous and GALS architectureLow power, eases DFS, removes chip level timing constraints

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ASC, a SystemC extension for modeling Asynchronous Systems, and its application to an Asynchronous NoC

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    1. ASC, a SystemC extension for modeling Asynchronous Systems, and its application to an Asynchronous NoC Cédric Koch-Hofer(1), Marc Renaudin(1), Yvain Thonnart(2), Pascal Vivet(2) (1) TIMA laboratory (CNRS-INPG-UJF), 46 Av. Félix Viallet, 38031 Grenoble – FRANCE (2) MINATEC, CEA-LETI, 17 rue des Martyrs, 38054 Grenoble – FRANCE {cedric.koch-hofer, marc.renaudin}@imag.fr {yvain.thonnart, pascal.vivet}@cea.fr

    2. Outline Asynchronous NoC and SystemC Asynchronous SystemC (ASC) Asynchronous NoC modeling Conclusion

    3. Context and Motivations Network On Chip High throughput, low power, scalability, modularity, QoS. Asynchronous and GALS architecture Low power, eases DFS, removes chip level timing constraints. Platform Modeling Offer to users high level modeling of new NoC protocols, Open framework / multi-abstraction level is required. => Use SystemC for Asynchronous NoC modeling

    4. Asynchronous Circuits modeling Asynchronous circuits modeling languages Modeled usually at handshake level, Dedicated languages: CHP, Haste (ex. Tangram), Balsa, Unknown to common designers. Standard HDL languages: Behavioral VHDL / Verilog extension, SystemC extension: sc_fifo, DTU (Technical University of Denmark) Channels, Do not respect delay insensitive circuit semantic. Objective Develop ASC, an extension to SystemC respecting the delay insensitive circuits semantic.

    5. SystemC overview SystemC is a C++ library for modeling and simulate complex systems at different level of abstraction. SystemC 2.2 is an IEEE (1666) standard. SystemC offers access to open framework modeling. A SystemC model is set of hierarchical modules interconnected by channels. Each module may contain: processes : define the behavior of the system. ports : communicating interface of the processes. channels : interconnect the different ports and define their communicating primitives. internal data : int, bool… Synchronization/communication between concurrent processes using events.

    6. SystemC limitations Main properties of asynchronous circuits: they use local handshaking protocols, they are insensitive to delays. Modeling asynchronous circuits with SystemC requires: blocking communication channels, memory-less communication channels, immediate event notifications, persistent event notifications. Standard SystemC channels do not respect these features. Modeling Asynchronous circuits requires special constructs and objects not available in SystemC.

    7. Outline Asynchronous NoC and SystemC Asynchronous SystemC (ASC) Asynchronous NoC modeling Conclusion

    8. ASC Core Language ASC library: a SystemC subset for modeling asynchronous circuits at handshake level. ASC primitives for hierarchical modeling: as_container, as_process : to declare modules. as_push, as_pull : to declare channels. as_{active|passive}_{in|out} : to declare ports. ASC primitives for communication and synchronization: send() : blocking send of data via an output port. receive() : blocking receive of data via an input port. idle(port1 | port2 | …) : waiting on a list of passive ports. nb_probe() : non blocking checking by passive ports if a communication was initiated.

    9. Non-Determinism modeling

    10. ASC Arbiter Example

    11. ASC Parallel Communication Allow to execute several parallel communicating actions in the same process. Parallel communication actions are triggered by one of the following methods: par_send for the input port, par_receive for the output port Definition of a method “idle” and an operator “||” for synchronizing a set of parallel communication actions.

    13. ASC Library implementation Add Primitive Channels: as_push, as_pull… Add Structural Elements: as_process, as_container… Add C++ constructs: as_choice_nd, as_guard…

    14. Outline Asynchronous NoC and SystemC Asynchronous SystemC (ASC) Asynchronous NoC modeling Conclusion

    15. ANoC Architecture 2D-Mesh based Topology, Wormhole Packet Switching, Static Source Routing, Virtual Channel for QoS, Nodes and Links use QDI asynchronous logic, Functional units use standard synchronous logic.

    16. ANoC protocol Wormhole protocol using 34 bit width flits. Packet signaling : 2 bits for signaling begin-of-packet (BOP) and its end (EOP). Static Routing using vector of dibits as path to the target. A dibit encodes the direction to follow for forwarding the flits of a packet.

    17. ANoC Node Architecture Node architecture: 5 Input Controllers : for flit routing. 5 Output Controllers : for flit arbitration. Fully Decentralized Arbitration: no global coordinator Fully implemented in QDI logic: 4-phase asynchronous protocol (WCHB), Delay Insensitive data encoding (multi-rail), All data flits are 4-rail encoded (to reduce Power Consumption).

    18. ANoC Node ASC Model Uses ASC SystemC library main primitives: as_push/as_pull: Communication channels. par_send/par_receive: Parallel communication primitives. as_guard/as_choice_nd: Deterministic & Non-deterministic choices. ANOC node ASC model: About 1500 lines, Validated using traffic generators in mixed level environment.

    19. ANoC Mixed-Level Validation

    20. Outline Asynchronous NoC and SystemC Asynchronous SystemC (ASC) Asynchronous NoC modeling Conclusion

    21. Conclusion ASC : an extension to SystemC for asynchronous circuits modeling: Validated on a real asynchronous NoC architecture, Using mixed-level/mixed-language SystemC simulation. Current developments: Specification of a model of time for ASC models, Implementation of trace facilities suited for ASC, Study how to perform asynchronous circuits synthesis from ASC/SystemC models.

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