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09/02/2012

Delay Chip Prototype & SPI interface. Joan Mauricio La Salle (URL) 15/02/2013. 09/02/2012. 1. Delay Chip Overview. Reset Block. rst. nRst. coarse. Mux. clkINT <3:0>. VCDL+Mux. clkT&H <3:0>. clkRef. Phase Comp + Charge Pump. nRst. Config. Status. SPI Slave.

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09/02/2012

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  1. Delay Chip Prototype & SPI interface Joan MauricioLa Salle (URL)15/02/2013 09/02/2012 1

  2. Delay Chip Overview Reset Block rst nRst coarse Mux clkINT<3:0> VCDL+Mux clkT&H<3:0> clkRef Phase Comp + Charge Pump nRst Config Status SPI Slave !en, clkdin, dout vControl<3:0> AnalogConfig coarse vControl clkADC<3:0> Digital Config VCDL+Mux LVDS Clock Config nRst CMOS Clock Slow Control 15/02/2013 2

  3. Delay Chip Features • SPI Slave interfaces withthe SPI Master and generates: • Register Select. • Read / !Write. • Serial Registers: • 16 Bits RW (Config. Registers). • 8 Bits RO (Status Registers). • 4 DLL Channels: • 1 PhaseComparator + ChargePump per Channel. • 2 Config. + 1 Status Register per Channel. • 3 independent LVDS Clk outputs per Channel.  24 pads!!! 15/02/2013 3

  4. Slow Control – SPI Slave • SPI Modes: • We are currentlyimplementingMode 1. 15/02/2013 4

  5. Slow Control – SPI Slave State Machine • SEU tolerant State Machine: • Hamming distance between Idle and critical states is 2. Idle state  spiEn = ‘0’ If 1-bit SEU occurs: E100, E100, E111 E101 Addr Dec Pump Rst Not in Idlestateafeterreset!!!! Reg Selection 14/01/2013 5

  6. Slow Control – SPI Slave Features • SPI Mode 1. • No ‘dead’ cycles between Addresses and Data. • Up to 64 Selectable Registers (32 Config. + 32 Status): • Only 8 Config. + 4 Status used in this chip. • SDI / SDO Bypass for troubleshooting purposes. • Charge Pumps can be reset via software. • SEU tolerant. • Area = 340x73 um2 . 15/02/2013 6

  7. Slow Control – SPI Addresses 15/02/2013 7

  8. Slow Control – Configuration Registers (16b) • RW Registers. • No state machine is required. • 16 Bits. • Signals: • Preset (Hardware) • Register Select • R/!W • Serial Clock • Serial Data Input • Serial Data Output (tristated) 15/02/2013 8

  9. Slow Control – Status Registers (8b) • RO status bits (no memory). • No state machine is required. • 8 Bits. • Signals: • Register Select • Serial Clock • Serial Data Output (tristated) 15/02/2013 9

  10. Slow Control – Conf. Reg. Write Simulation • Write = 0x9A31. 1 0 0 1 1 0 1 00 0 1 1 0 0 0 1 1000001000000001 11010001 15/02/2013 10

  11. Slow Control – Conf. Reg. Read Simulation • Read = 0x9A31. 1 0 0 1 1 0 1 00 0 1 1 0 0 0 1 1 0 0 1 1 0 1 00 0 1 1 0 0 0 1 1000001000000001 15/02/2013 11

  12. Slow Control – Status Reg. Read Simulation • Read = 0xD1. 1 1 0 1 0 00 1 1010101010101010 15/02/2013 12

  13. Delay Chip Prototype • NextRun @ 13/03/2013 – Europractice. • New test board (AnalogMezzanine) isbeingdesigned. • Somechangesneeded in the FEB FPGA: • SPI Mastercapability (opencores.org). • Interface between CAT and SPI block. • 4 Pins needed (5 iftheboard has two SPI Slaves). 15/02/2013 13

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