IAY 0600 Digitaalsüsteemide disain

1. Alexander Sudnitson Tallinn University of Technology IAY 0600Digitaalsüsteemide disain Course Overview

2. Administrative Aleksander Sudnitsõn Arvutitehnika instituut, dotsent IT-309 alsu@cc.ttu.ee www.pld.ttu.ee/~alsu IAY0600 Digitaalsüsteemide disain (erikursus) IAY0600 Digitaalsüsteemide disain (PRAKTIKUM) IAY0120 ARVUTITEHNIKA PROJEKT

3. Administrative • Loengute õppetöö keel: inglise • Loengud: • neljapäeviti 14.00 - 15.30 • Praktikum: IT-307 Dimitri Mihhajlov • 16.00 - 17.30 • esemine regulaarne praktikum toimub 18.02.2010 (pärast registreerimist)

4. Hindamine Teoreetiliste teadmiste osakaal eksamil on 40% hindest ja projekteerimisülesannete tulemuste demonstratsioon koos lahenduste seletuskirjaga annab 60% eksamihindest. “LEARNING BY DOING”

5. Õppeaine sisu lühikirjeldus Digitaalsüsteemide projekteermis-metoodika VHDL ja prgrammeeritava loogika (FPGA) abil. Realiseerimine väliprogrammeeritaval loogikal (FPGA). Digitaalseadmete kiire prototüüpimine. Asünkroonsete süsteemide põhialused (süsteemne vaade).

6. Õppekirjandus Iga tudeng saab komplekti slaide enne loengut. K. L. Short, VHDL for Engineers, Pearson Education, Inc., 2009. Sparso J. and Furber S. Principles of Asynchronous Circuit Design: a Systems Perspective. Boston: Kluwer, 2001. P.P. Chu, FPGA Prototyping Using VHDL Examples: Xilinx Spartan-3 Version, Jonh, Willey & Sons, 2008. J. O. Hamblen, T.S. Hall, and M. D. Furman, Rapid Prototyping of Digital Systems, Springer, 2007.

7. Alexander Sudnitson Tallinn University of Technology IAY 0600Digitaaltehnika erikursus VHDL/PLD Design Methodology

8. Inputs Outputs Discrete System Digital System A discrete system is a system in which signals have a finite number of discrete values. (This contrasts with analog systems, in which signals have values from an infinite set). Any finite number of discrete values can be represented by a vector of signals with just two values. Such a signal, which takes only two values, is called a digital signal (or binary, or logic), and any device that processes digital signals is called a digital device.

9. Specification (behaviour) Analysis (verification) Synthesis Implementation (structure) Design process The design process consists of obtaining an implementation that satisfies the specification of a system. The analysis of a system has an objective the determination of its specification from an implementation. The synthesis consists of obtaining an implementation that satisfies the specification of a system

10. Different design views Systems can be described from different points of view: Behavior: what does it do? Structure: what is it composed of? Functional properties: how do I interface to it? Physical properties: how fast is it?

11. Design Representation Three different domains of description: A behavioral or functional representation is one that looks at the design as a black box. A behavioral representation describes the functionality but not the implementation of a given design, defining the black box’s response to any combination of input values but without describing a way to design or build the black box using the given components. A structural representation is one that the black box as a set of components and their connections. It specifies the product’s implementation without explicit reference to its functionality. In some cases, the functionality could be derived from that of its interconnected components. A physical representation is one that specifies the physical characteristics of the black box, providing the dimensions and locations of each component and connection contained in the structural description. The physical representation is used to describe the design after it has been manufactured, specifying its weight, size, heat dissipation, power consumption and the position of each input or output pin.

12. Behavior Description Structural Description System Processes Programmable cores, IPs, ASICs Architectural Algorithm Processor, Memory, Peripheral interface Register Transfer (RTL) Dataflow Registers, Adders, Multipliers, etc. Logic Boolean equations Logic netlist, Schematic View Modified Y Chart: levels of abstruction

13. Time Units Structural Description Behavior Description Processes Comuncation Transaction Programmable cores, IPs, ASICs Computation Step Algorithm Processor, Memory, Peripheral interface Clock Cycle Dataflow Registers, Adders, Multipliers, etc. Boolean equations Logic netlist, Schematic Delay View Timing units at different levels

14. Behavior Description Structural Description View Modified Y Chart : this course area Synthesis Analysis Processor, Memory, Peripheral interface Algorithm Registers, Adders, Multipliers, etc. Dataflow / RTL Boolean equations Logic netlist, Schematic

15. Behavior Description Structural Description View Transformations Modified Y Chart: transformations Algorithmic Processor, Memory, Peripheral interface Algorithm Register-Transfer Registers, Adders, Multipliers, etc. Dataflow Logic Boolean equotions Logic netlist, Schematic

16. Behavior Description Structural Description Behavioral synthesis RTL synthesis Logic synthesis View Chart supporting synthesis activity Algorithmic level of abstraction Register-transfer level of abstraction Logic level of abstraction

17. Behavior Structure A B Sum Carry Sum A 0 0 0 0 Carry B HalfAdder 0 1 1 0 1 0 1 0 1 1 0 1 A Sum  & Carry B Example: HalfAdder Sum = ¬A&B  A&¬B = A  B Carry = A & B

18. Sum A HalfAdder B Carry architecture RTL of HALFADDER is begin SUM <= A xor B; CARRY <= A and B; end RTL; Example: HalfAdder Behavioral Description Sum = ¬A&B  A&¬B = A  B Carry = A & B entity HALFADDER is port(A, B: in bit; SUM, CARRY: out BIT); end HALFADDER; This is data flow behavioral description

19. Design flow for VHDL/PLD design methodology

20. The half-adder UUT and its testbench