Methods to Differentiate Mil/Aero Solutions Using FPGAs BOF session W – Focus on verification

1. Methods to Differentiate Mil/Aero Solutions Using FPGAsBOF session W – Focus on verification Dan Gardner Final MAPLD BOF Presentation

2. Requirements for FPGA Software in Mil/Aero • Cost effective delivery of mission performance • Initial Creation • Cost and speed of design • Predictable time to market at fixed cost • Fast iterations • Timing and system closure • Complete Verification • Commercial FPGA often skips many verification steps • Some Mil/Aero applications have additional considerations • Maintenance of Project • Cost of life cycle maintainability of design • Support of standard platforms • Support Mil-preferred devices, documentation and flows Gardner MAPLD 2005/P145_BOF-W

3. Technologies to Consider • All technologies listed below are required to build a complete methodology and will be covered • This presentation will essentially focus on the unique requirements of Mil/Aero FPGA applications: • Rule checker with platform-independent coding styles • Design management • RTL + physical synthesis • I/O design with integration path to PCB • System-level design • Verification • Electronic System-Level (ESL) Overview • Assertion based (CDC to validate SEU protection) • Coverage driven • Clock domain crossing (CDC) • Embedded systems Gardner MAPLD 2005/P145_BOF-W

4. Verification Technology • Rule checker with platform-independent coding styles • Design management • Verification • Electronic System-Level (ESL) Overview • Assertion based (CDC to validate SEU protection) • Coverage driven • Clock domain crossing (CDC) • Embedded systems Gardner MAPLD 2005/P145_BOF-W

5. Rule Checkers Static Design Checking for VHDL/Verilog RTL • Encapsulate knowledge: • Expect built-in checks from standard sources • Reuse Methodology Manual • FPGA vendor recommendations • Must allow quick customization for your own checks • Use Early and Often: • Perform checking interactively or in batch • Understand the causes of violations • Easily interact, organize, & track violations • Interactively trace & fix violations • Share knowledge: • Share checks with the team/company • Allow any designer to apply accumulated knowledge • Export results for reporting Gardner MAPLD 2005/P145_BOF-W

6. Design / Document Verification Synthesize Rule Checking & Project Management • HDL Designer: Manage Text, Graphics, VHDL, Verilog, SystemC, SystemVerilog, PSL, C/C++, Scripts, Revision Control, Automated Design Documentation Process Automation Version Management PCB – I/O Designer Gardner MAPLD 2005/P145_BOF-W

7. Verification Technology • Rule checker with platform-independent coding styles • Design management • Verification • Electronic System-Level (ESL) Overview • Assertion based (CDC to validate SEU protection) • Coverage driven • Clock domain crossing (CDC) • Embedded systems Gardner MAPLD 2005/P145_BOF-W

8. Design Languages & Tasks Task Language Text / UML Requirements HVLs extend & accelerate the RTL design processand enable RTL designers to cross the chasm to system level design C/C++ Untimed SystemC Algorithm Exploration Transaction Level SystemC Architecture Analysis System Verilog Verification Assertions PSL/SVA VHDL Verilog RTL Design Gardner MAPLD 2005/P145_BOF-W

9. 20x (2 days!!) 10,000x (1 min) Functional 1,000x Structural 100x Transaction 10x 2x (2 weeks) Cycle 1x (7 days) 1x (5 weeks) RTL Abstraction Drives Design Productivity Implementation Simulation Source Algorithmic C++ Untimed TLM SystemC Timed TLM SystemC Cycle Accurate SystemC RTL Gardner MAPLD 2005/P145_BOF-W

10. Automatic Generation of Verification Infrastructure Original C++ Testbench • Facilitates the verification of the synthesized design • The original C++ testbench can be reused to verify the design • RTL or cycle accurate • SystemC, VHDL or Verilog • Transactors convert function calls to pin-level signal activity • Pushbutton verification solution includes Makefiles and simulation scripts Transactor RTL Original C++ Algorithm Transactor Comparator Golden results DUT results Gardner MAPLD 2005/P145_BOF-W

11. Quickly produce RTL code from algorithmic specifications Regardless of the quality of the architecture Run RTL synthesis and P&R with integrated tool flows Validate the functional correctness of the algorithm on FPGA prototyping boards Architecture optimization can be pursued in parallel Exhaustive Algorithm VerificationWith Automated Real Time Prototypes ? Algorithms C Code Constraints Catapult C Synthesis Precision RTL Synthesis RTL Code Constraints FPGA Vendor P&R Netlist Constraints  Prototyping Gardner MAPLD 2005/P145_BOF-W

12. Catapult C Addresses the ESL Synthesis Challenge Typical RTL Design Flow Algorithm Functional Description MATLAB SPW C/C++ Floating Point Model Floating Point Model System Designer Fixed Point Model Fixed Point C++ Model + Catapult C Synthesis Constraints Micro-architecture Definition RTL Synthesis + Logic Analyzer Place & Route Manual Methods RTL Design Hardware Designer Hardware ASIC/FPGA RTL Area/Timing Optimization RTL Synthesis Precision RTL or DC Logic Analyzer Place & Route Vendor ASIC or FPGAVendor Hardware ASIC/FPGA NEW Catapult C Design Flow Algorithm Functional Description • Safer design flow • Shorter time to RTL • More efficient methodology • Design optimized to system requirements through incremental refinement Gardner MAPLD 2005/P145_BOF-W

13. Methodology Explosion Targeting Verification • Assertion-based verification • Functional coverage • Constrained-random testing • Coverage-driven verification • Dynamic-formal verification • Transaction-level verification • Model checking • And more . . . Gardner MAPLD 2005/P145_BOF-W

14. Common Verification Methodologies Gardner MAPLD 2005/P145_BOF-W

15. SystemVerilog for Verification • SystemVerilog is a complete Verification Language • Can be used with VHDL • Stimulus generation capabilities • Dynamically configurable constrained-random value generation • Ability to generate constrained-random stimulus sequences • Ability to randomly select control paths (test scenario selection, etc.) • Functional coverage modeling • Measure the verification quality and test effectiveness • Dynamic reactivity with constrained-random stimulus generation • Assertion-based verification • Property specification • Assertion & coverage monitoring • High-level modeling (programming) capabilities • Efficiently and effectively model the operational environment • Develop reusable verification environments Gardner MAPLD 2005/P145_BOF-W

16. Assertion-Based VerificationAssertions Enable Higher Quality Designs Reference Model • Assertions provide observability for higher complexity designs • ABV makes assertions a key element, ensuring that design properties are not violated • Assertions describe (un)desired behavior • Assertions dramatically shorten debug and repair time • Assertions stay on during block, chip and system-level tests • Finds bugs you weren’t looking for Bus Monitor Bus Monitor Assertion Checkers Assertion Checkers Gardner MAPLD 2005/P145_BOF-W

17. Expect Widespread Use of Coverage-Driven Verification • PSLand SystemVerilog provide coverage constructs • Simulators integrating functional coverage to improve performance and debug • New test strategies require functional coverage • Random and constrained random tests need coverage to determine what they tested Gardner MAPLD 2005/P145_BOF-W

18. Clock-Domain Crossings • Incorrect handling of Clock-Domain Crossing (CDC) signals is the 2nd major cause of re-spins • Traditional verification techniques do not work for CDC signals • CDC problems are subtle, will occur in hardware, and are complex to debug Assertion Synthesis automates CDC verification, significantly reducing the risk of CDC-related silicon re-spins Gardner MAPLD 2005/P145_BOF-W

19. Assertion Based Verification Automation: Assertion Synthesis IP: CheckWare Engine: Questa-AFV Language: SVA and/or PSL Complete Verification Flow Gardner MAPLD 2005/P145_BOF-W

20. Verification Technology • Rule checker with platform-independent coding styles • Design management • Verification • Electronic System-Level (ESL) Overview • Assertion based (CDC to validate SEU protection) • Coverage Driven • Clock domain crossing (CDC) • Embedded systems Gardner MAPLD 2005/P145_BOF-W

21. Platform FPGAs Need a Complete Flow Hardware Software Platform Studio IDE Platform Exp ASAP Precision Synthesis Inventra Stacks Code|Lab ISS Seamless Modelsim BSP ISE Tools Microtec Nucleus XRAY SW-HW OnChip Debug Chipscope PCB, Signal Integrity Tools Gardner MAPLD 2005/P145_BOF-W

22. Supports: Edit/Compile/Verify Eliminates: Edit/Synthesize/ Implement/Download/Verify Promotes: Superior Visibility and Control Evaluation Board Seamless FPGA Co-Verification HW/SW Co-verification: Faster Iteration Loop Without Co-verification With Co-verification HDL Entry HDL Entry HDL Compile Synthesis Implementation Download Bitstream Into FPGA Gardner MAPLD 2005/P145_BOF-W

23. Summary • With engineers from software, hardware and system disciplines all converging on FPGAs, it is important to focus on the methods that can help differentiate your solution from others. • It is necessary to use all the basic verification and design tools, but there are new technologies emerging that can better address the unique requirements of Mil/Aero applications. Gardner MAPLD 2005/P145_BOF-W