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YO! - A Time-of-Arrival Receiver for Removal of Femtosecond Helicity-Correlated Beam Effects *

YO! - A Time-of-Arrival Receiver for Removal of Femtosecond Helicity-Correlated Beam Effects *. J. Musson † , T. Allison † , A. Freyberger † , J. Kuhn ¶ , B. Quinn ¶ † TJNAF, Newport News, VA, 23606, USA ¶ Carnegie-Mellon University, Pittsburgh, PA, 15213, USA.

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YO! - A Time-of-Arrival Receiver for Removal of Femtosecond Helicity-Correlated Beam Effects *

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  1. YO! - A Time-of-Arrival Receiver for Removal of Femtosecond Helicity-Correlated Beam Effects* J. Musson†, T. Allison†, A. Freyberger†, J. Kuhn¶, B. Quinn¶ †TJNAF, Newport News, VA, 23606, USA ¶Carnegie-Mellon University, Pittsburgh, PA, 15213, USA

  2. Parity violation experiment for protonic quark structure G0 Experiment

  3. Problem 1: Phasing TOA • Concept: Lock 499 MHz to coincide with arrival of G0 beam. Look for timing differences associated with different helicity orbits. • Easy, but……! • G0 Beam structure only fills every 16th bucket. 31 MHz subharmonic at –95 dBm • Available beamline components respond to either microwave or audio! • 100 ps window with ~100 us settling time

  4. Problem 2: Phase Ambiguity • 499 MHz and 1497 MHz produce 16 and 48 zero-crossings per trigger event, resulting in cycle ambiguity of 2Pi/n. Simple pre-scaling not feasible. • Zero-th “bin” must be located (and tracked during LOL) to +/- 334 ps.

  5. Sampling-Receiver System

  6. Equivalent time sampling Courtesy Tektronix Corp. Modern SPD….. (courtesy Metelics, Inc.) Sampling Phase Detector

  7. SPD • PECL-based SPD has < 100 ps risetime and < 1 ps cycle-to-cycle jitter. • Exceptional temperature stability wrt decision logic threshold ultimately sets sample resolution to ~1 ps. Courtesy AD Automation, Inc.

  8. Receiver

  9. Real Hardware….. • SPD and 31 MHz PLL/Tracking filter

  10. Real Hardware (cont.) • Receiver Chassis

  11. Baseband DSP Processor • Loop IIR, PID, and Timing functions

  12. IIR + PID (Two Loops)

  13. PID • SystemView (MATLAB) used to conjure initial P, I, and D constants for each loop. • Ziegler-Nichols “employed” to optimize for 0.5 damping with 100 us risetime. Timing and Loss-of Lock

  14. Bench Testing

  15. Bench Testing (31 + 499 loops)

  16. Bench Testing (Sensitivity) • 1 ps 30 Hz delay easily recognizable with > 10 dB S/N. Subsequent tests showed 10 fs MDS.

  17. Commissioning Tests

  18. Production Data (Timing vs. I)

  19. Production Data (Timing vs. Position)

  20. Old principles never die! Easily extended to high-BW ADCs PECL SPD reliable and easy to construct FPGA radiation resistant (for FLASH)! Other Applications: Multi-freq VVM DC at Cavity Thank you!!!!!!!!! Conclusion, Parting Shots….

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