Graduate Computer Architecture I

1. Graduate Computer Architecture I Lecture 15: Intro to Reconfigurable Devices

2. Quick Review Digital Logic

3. Typical Circuit (Full-Adder)

4. NAND

5. Full-Adder Using NAND A B C’ S C

6. VLSI Layout of NAND Full-Adder

7. Full-Adder Using Array of Logics S C’

8. Programmable Logic (PLA/PAL/PLD)

9. More Complex Programmable Logic

10. Programmable Logic Inexpensive One-time Programmable Devices BURN it once and use! Complex Programmable Logic Devices

11. Full Adder Using Memory 8 by 2-bit Memory 3bit Address Concat(C’,A,B) Addr 2bit Data Concat(S,C) Data

12. Simple Wire Switch (4x4 Crossbar) Input Ports Output Ports

13. Field Programmable Gate Array

14. Logic Block (Xilinx Virtex 4000) SRAM based Logic (4 input Look-up-table) Registers

15. FPGA Architecture

16. Design Flow DESIGN ENTRY RTL HDL EDITING CORE GENERATION RTL HDL-CORE SIMULATION SYNTHESIS IMPLEMENTATION TIMING SIMULATION FPGA PROGRAMMING & IN-CIRCUIT TEST

17. HDL Design Flow Language Construct Templates RTL HDL Files HDL Module Frameworks Accessed within HDL Editor DESIGN WIZARD LANGUAGE ASSISTANT HDL EDITOR

18. IP Core Generation HDL instantiation module for core_name Select core and specify input parameters CORE GENERATOR EDIF netlist for core_name Other core_name files

19. Functional Simulation HDL instantiation module for core_names EDIF netlists for core_names Set Up and Map work Library RTL HDL Files Testbench HDL Files Compile HDL Files Test Inputs or Force Files MODELSIM Functional Simulate Waveforms or List Files

20. Synthesis EDIF netlists for core_names All HDL Files Edit FPGA Express Synthesis Constraints Select Top Level Synthesis/Implement-ation Constraints Select Target Device FPGA EXPRESS Synthesize Gate/Primitive Netlist Files (EDIF or XNF) Synthesis Report Files

21. Implementation Gate/Primitive Netlist Files (XNF or EDN) Netlist Translation XILINX DESIGN MANAGER Map Place & Route Model Extraction Timing Model Gen HDL or EDIF for Implemented Design Create Bitstream Standard Delay Format File BIT File

22. Timing Simulation HDL or EDIF for Implemented Design Standard Delay Format File Set Up and Map work Directory Testbench HDL Files Compile HDL Files MODELSIM Test Inputs, Force Files Compiled HDL HDL Simulate Waveforms or List Files

23. Programming FPGA Bit File Input Byte GXSLOAD GXSPORT FPGA Other Inputs Outputs

24. Emergence of FPGA • Great for Prototyping and Testing • Enable logic verification without high cost of fab • Reprogrammable  Research and Education • Meets most computational requirements • Options for transferring design to ASIC • Technology Advances • Huge FPGAs are available • Up to 200,000 Logic Units • Above clocking rate of 500 MHz • Competitive Pricing

25. System on Chip (SoC) • Large Embedded Memories • Up 10 Megabits of on-chip memories (Virtex 4) • High bandwidth and reconfigurable • Processor IP Cores • Tons of Soft Processor Cores (some open source) • Embedded Processor Cores • PowerPC, Nios RISC, and etc. – 450+ MHz • Simple Digital Signal Processing Cores • Up to 512 DSPs on Virtex 4 • Interconnects • High speed network I/O (10Gbps) • Built-in Ethernet MACs (Soft/Hard Core) • Security • Embedded 256-bit AES Encryption

26. Computational Density Higher number means greater efficiency

27. Potential Advantages of FPGAs

28. Summary • Rapidly changing platform • Ten thousand times in silicon chip capacity • Cost did not increase that much • Same designs • Von Neuman architecture time-multiplexes • Old processor designs, only smaller • Not much innovations • Programmable SW/HW Platforms • General Computing Systems do not have to look like traditional processors • Future?