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TFT LCD AIM SPICE

TFT LCD AIM SPICE. P92943013 / 梁亦中 P91943014 / 方貴弘. Past History of SPICE. Shell. Smart SPICE. AIM-SPICE. Kernel Berkeley SPICE. HSPICE. PSPICE. Spectre. Eldo. SPICE : S imulation P rogram with I ntegrated C ircuit E mphasis

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TFT LCD AIM SPICE

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  1. TFT LCD AIM SPICE P92943013 / 梁亦中 P91943014 / 方貴弘

  2. Past History of SPICE Shell Smart SPICE AIM-SPICE Kernel Berkeley SPICE HSPICE PSPICE Spectre Eldo • SPICE : Simulation Program with Integrated Circuit Emphasis • 1968 : Ron Rohrer Berkeley,Larry Nagel CANCER • 1970 : SPICE1(Fortran) • 1975 : SPICE2(Fortran) • 1980 : SPICE3(C Language) • 1980~Now : • HSPICE • PSPICE • AIM-SPICE (AIM) • Smart-SPICE (Silvaco) • Eldo (Mentor) • Spectre (Cadence)

  3. SPICE Algorithms Principle : Kirchhoff’s Law node Numerical analysis : Newton Method

  4. Analog Circuit Design Flow Schematic edit Circuit simulation SPICE Schematic driven layout Layout -Laker Device model extraction 1. TEG data analysis 2. Curve fitting 3. Process characterization DRC/LVS -Calibre No Yes Post simulation SPICE Parasitic R/C Extractor -Calibre RCX GDS II / Mask

  5. AIM SPICE Parameter Extract_1 Modeled Measured TFT LCD Test Mask IV Curve IdVd Curve Vg = 5V,10V,15V,20V,30V IdVg Curve Vd = 1V,4V,7V,10V,13V

  6. AIM SPICE Parameter Extract_2 Extract Parameter Hole-Induced Leakage Current Above Threshold Below Threshold

  7. AIM SPICE Parameter Extract_3

  8. Pixel Equal Circuit & RC Calculation L1 W1 1 5 2 6 L2 9 8 10 3 4 7 W2 Cgate =((Cst*Clc)/(Cst + Clc) + Cgs + Cgs_coup + Cdg cross + Cgate_com)*1280*3 Rgate =(ρ * L1/W1)*1280*3 Cdata =Cgd + Cdg cross + Cdata_com + Cpixel_data_coup)*1024 Rdata=(ρ * L2/W2)*1024 Cpixel = Cgs + Cgs_coup + Clc + Cst + Cpixel_data_coup Data Line the N-1th Data Line the N th Gate Line the (N-1)th C lc C st(on gate) 2 1 C pixel_data coup(own) 9 C data_com ( lc ) 6 C pixel_data coup(next) 10 Gate Line the Nth C gs C gs_coup C gd 8 3 4 C gate_com 5 C dg cross 7

  9. Using Pi(π) Model to Simulated R One πmodel C We using 4 π Model to simulated one gate line and data line

  10. Panel Equal Circuit of Simulation 1 2 6 7 8 If Resolution = 1280*1024 Node 3 = Sub_pixel (0,512) Node 4 = Sub_pixel (1920,512) Node 5 = Sub_pixel (3840,512) Signal in 1 14 V Driving Direction Gate n-1 Pulse 2 10 11 12 V 23 26 Gate n Pulse 3 4 5 V 17 20 6 7 8 9 9 9

  11. (Device+Name) Node Value / Parameter SPICE Program Description 1 - Basic Definition Device: D: Diode C: Capacitance I: Independent Current Source J: JFET M: MOS Q: BJT R: Resister V: Independent Current Source ex:Rgate 1325k Cgate1325p Vgate1325V M1 2(D)3(G)6(S)0(GND) Model()

  12. SPICE Program Description 2 - Basic Definition Dot Command Format => . command .DC 直流掃描 .END 檔案結束 .IC 設定起始電壓電流 .MODEL MODEL宣告 .PLOT 輸出圖形 .PRINT 輸出數值 .TRAN 暫態分析

  13. SPICE Program Description 3 – Power definition VGATE1 3 0 PWL 0u vgl 25u vgl 25.01u vgh 35.31u vgh 35.32u vgl 150u vgl VSIG1 2 0 PULSE (vdl vdh 12.5u 1n 1n 12.499u 25u) V1V2startrise fallpulse widthperiod VCOM2 9 0 5V 5V DC voltage source V2 V1

  14. 6 3 7 5 0 4 SPICE Program Description 4 - Example 1 *** Simulation of One Gate Delay by AIM-Spice *** .param vgh=27V vgl=-6V vgc=-6V .param gpi_r=1.176k gpi_c=24.27p .param gpx_r=0.3k .param length=9u width=18u VGATE1 3 0 PWL 0u vgl 25u vgl 25.01u vgh +35.31u vgh 35.32u vgl 150u vgl .IC V(10)=vgl V(3)=vgl ***GATE DELAY 0 *** Drive IC RGATE01 0 3 gpx_r CGATE01 0 3 2.5p CGATE02 0 10 2.5p ***GATE DELAY 1 *** PI-g1 RGATE11 3 6 gpi_r RGATE12 6 4 gpi_r CGATE11 3 0 gpi_c CGATE12 6 0 gpi_c*2 CGATE13 4 0 gpi_c ***GATE DELAY 2 *** PI-g2 RGATE21 4 7 gpi_r RGATE22 7 5 gpi_r CGATE21 4 0 gpi_c CGATE22 7 0 gpi_c*2 CGATE23 5 0 gpi_c .TRAN 1.000000e-07 100u .PLOT TRAN V(3) V(4) V(5) .END

  15. SPICE Program Description 5 - Model - 1 General form: MXXXXXXX ND NG NS NB MNAME<L=VALUE> <W=VALUE> <AD=VALUE> + <AS=VALUE> <PD=VALUE> <PS=VALUE> <NRD=VALUE> + <NRS=VALUE> <OFF> <IC=VDS,VGS,VBS> <TEMP=T> a-Si TFT in SMART SPICE .MODEL TFT  NTFT(LEVEL = 35, ******* ) a-Si TFT in AIM SPICE .MODEL TFT NMOS(LEVEL = 15, ******* )

  16. Example of a-Si TFT Description by AIM Spice SPICE Program Description 6 - Model - 2 M1 2 3 6 0 TFT L=length W=width .MODEL TFT NMOS ( LEVEL = 15 TOX = 3.5E-7 +TNOM = 27 VTO = 1.6 +ALPHASAT= 0.8101843 DEFO = 0.598965 DELTA = 9.2 +EL = 1.1 EMU = 0.06 EPS = 11 +EPSI = 4.7 GAMMA = 0.3709371 GMIN = 3.98107E22 +IOL = 6.30957E-14 KASAT = 1E-3 KVT = -0.036 +LAMBDA = 0 M = 1.1733413 MUBAND = 1E-3 +SIGMAO = 3.16228E-15 VO = 0.37 VAA = 3.117726E4 +VDSL = 15 VFB = -2.41736 VGSL = 100 +VMIN = 0.797118 CGDO = 0.6n CGSO = 0.6n )

  17. SPICE Program Description 7 - Example 2 *** Simulation of One Pixel By AIM-Spice *** .param vgh=27V vgl=-6V .param vdl=1V vdh=10V .param gpx_r=0.3k .param lcc=0.179p csc=0.164p cgsc=0.0078p .param length=9u width=18u VGATE1 3 0 PWL 0u vgl 25u vgl 25.01u vgh 35.31u + vgh 35.32u vgl 150u vgl VGATE2 10 0 vgl VSIG1 2 0 PULSE (vdh vdl 12.5u 1n 1n 12.499u 25u) VCOM2 9 0 5V .IC V(10)=vgl V(3)=vgl V(9)=5V .IC V(2)=vdh .IC V(6)=vdl RGATE01 0 3 gpx_r RGATE02 0 10 gpx_r CGATE01 0 3 2.5p CGATE02 0 10 2.5p CLC1 6 9 lcc Cs1 6 10 csc CGS1 3 6 cgsc ***TFT*** M1 2 3 6 0 TFT L=length W=width * SiOx thickness 3500A .model TFT NMOS(level=15 alphasat=0.715 defo=0.6 delta=5 emu=0.02 + el=0.1 eps=11 epsi=4.7 gamma=0.535 gmin=1e+023 iol=2.8e-012 + kvt=-0.01 lambda=0.001 m=1.2 muband=0.001 rd=220000 rs=220000 + sigmao=5e-014 tnom=27 tox=3.5e-007 vaa=2400 vdsl=30 vfb=-5.38 + vgsl=50 vmin=0.3 vo=0.29 vto=1.8 ) .TRAN 1.000000e-07 100u .PLOT TRAN V(2) V(3) V(6) .END

  18. SPICE Output Node Waveform • What can we gain from this Waveform Chart? • Gate Delay • Charging Capability • Feedthrough Voltage

  19. Gate Delay Simulation Data 17” Gate Delay at charge time 10.3us Gray level = L0 (black) Gate Delay(at Vg=0V) Measured=1.2us Simulated=1.2us

  20. Other Case about SPICE Simulation_1 19” Gate Pulse Cut (Cs on Com)

  21. Other Case about SPICE Simulation_2-1 dVcom = (dVp_P + dVp_N)/2

  22. Other Case about SPICE Simulation_2-2  Modify = Simulation * 1.5 17 inch

  23. Other Case about SPICE Simulation_3 Cpd Coupling Effect Simulation

  24. LCD Circuit for Smart Spice ( Orcad )

  25. LCD Pixel Circuit for Smart Spice Pixel Capacitance Clc=0.139pF Cst=0.229pF Cgs=0.011pF Cpd_L=0.012pF Cpd_R=0.010pF Rlc=10E12ohm Other Capacitance Cgc=0.009pF Cdc=0.022pF Cgd=0.056pF

  26. The End

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