Understanding Serial Data Transmission: SPI vs. RS232

1. ELE22MIC Lecture 12 & 13 • Serial Communications • Serial Data Formats • SPI • RS232 • HC-COM’s Serial Port - 6850 • Sample Interrupt Service Routine (ISR) • IBM PC - 16550 • RS232 / ITU V.24 / EIA232 • Chip Select Logic - Revision of Problem Class

2. Serial Data Transmission (1) • Serial I/O is the transmission of data over a single communication line. • Cheaper than parallel • Data is moved sequentially one bit at a time. • Requires a conversion from parallel data format to serial format. • This concersion is normally performed by a shift register driven by a clock.

3. Serial Data Transmission (2) • At the receiving end, data must be reconstructed back into parallel format. • Some method is required to identify bit boundaries. • i.e.: how do you differentiate between 000 and 0000?

4. Serial Data Transmission (3) • Two methods: • Synchronous Transmission • Use a common clock to synchronise the receiver with the transmitter. • Therefore requires a separate tine to carry the clock. • Asynchronous Transmission • The receiver and transmitter has separate, independent, accurate local clocks.

5. Synchronous Serial Data Transmission(4) • Synchronous Transmission is used with the Serial Peripheral Interface (SPI) • Uses 4 wires: • Clock • Data • Select • Ground

6. Serial Peripheral Interface (SPI 1) During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line synchronises shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. On a master SPI device, the slave select line can optionally be used to indicate a multiple-master bus contention.

7. Serial Peripheral Interface (SPI 2) The SPI can be used to add an extra 8 bit output port using an 8-bit shifter and latches. MasterOutSlaveIn MOSI (Serial Data) -> Pin14 (MSB sent first) Clock ->Pin 11 SS# = Pin 12 = Low during transmission Reset# = Pin 10 = 5V OE# = Pin 13 = 0V

8. Serial Peripheral Interface (SPI 3) Transfer Format Data Out Clocked with Rising SCLK

9. Serial Peripheral Interface (SPI 4) ACCESS_SPI: LDAA #50 ; 0101 0000 STAA 1028 ; SPI Control Register (SPCR) LDAA #38 ; 0011 1000 STAA 1009 ; DDRD LDAA #55 ; 0101 0101 STAA 102A ; SPDR LDAB 1029 ; SPSR BITB #80 ; SPIF bit BEQ B7C2 ; LDX #1000 ; BCLR 08, X 20 ; 1008 = Port D = Strobe Bit 3 Low BSET 08, X 20 ; 1008 = Port D = Strobe Bit 3 High BRA ACCESS_SPI

10. Asynchronous Serial Data Transmission(1) • RS232 Voltage Levels & Data Format • Line Transciever with Charge Pump - • the MAX232 series. • Serial Data Format • Start Bit, Data Bits, Parity, Stop Bits • Errors: Framing, Overrun, False Start • The 6850 ACIA (Asynchronous Communications Interface Adapter) • AKA: UART (Universal Asynchronous Receiver Transmitter) or ACE (Asynchronous Communications Element) • The RS232 Transmission Distance Limits

11. RS232 : Clock Synchronisation (1) • The receiver phase locks its local clock to the transmitter's clock by detecting the start and stop of a serial frame. • Thus it does not require a separate clock line as the data line contains timing information.

12. RS232 Asynchronous Data Transmission - Data Format

13. RS232 : Communication Speed • The rate at which data is transmitted is called the bit-rate • Bit-rate is measured in bits per second. • In modems tones of different frequencies are used to represent different bits. • Baud rate refers to the frequency of the carrier used to transmit the serial data. (includes synchronisation items: start bit & stop bits)

14. RS232 : Bit Sampling • The signal is sampled by the ACIA in the middle of each bit period.

15. RS232 : Bit Error Detection • In any data transfer there is the potential for bit-errors. Parity can be used as a check that the correct bit pattern is received. • Parity calculation involves adding the “1” bits in a frame together. • Even Parity • Adding all bits in frame + parity => ‘0’ • Odd Parity • Adding all bits in frame + parity => ‘1’

16. RS232 : Bit Error Detection

17. RS232 : Clock Synchronisation (2) • Start bit signifies the beginning of the frame • Stop bit(s) identify the end of the frame • If the stop bits are received incorrectly it is assumed that the receiver’s clock has drifted out of phase, or some other error has occurred, and a FRAMING ERROR is declared

18. 6850 : Status Register 0 RDRF Receive Data Register Full 1 TDRE Transmit Data Register Empty 2 DCD Data Carrier Detect 3 CTS Clear To Send 4 FE Framing Error 5 OVRN Receiver Overrun 6 PE Parity Error 7 IRQ IRQ pending

19. 6850 : Bus Interface

20. 6850 : Control Register Clock divisor: 0 Counter Divisor Select 1 1 Counter Divisor Select 2 Communication Settings: 2 Word Select 1 3 Word Select 2 4 Word Select 3 Interrupt Control: 5 Transmit Control 1 6 Transmit Control 2 7 Receiver Interrupt Enable

21. 6850 : Configuration - Divisor An ACIA may be configured to suit a range of serial communications formats by setting the appropriate bits in the control register Clock divisor: Control Register bits CR1, CR0 CR0 Counter Divisor Select 1 CR1 Counter Divisor Select 2 CR1 CR0 Description 0 0 divide by 1 0 1 divide by 16 1 0 divide by 64 1 1 Master reset

22. 6850 : Configuration - Word Format Data word format Settings: CR2 Word Select 1 CR3 Word Select 2 CR4 Word Select 3 CR4 CR3 CR2 Description 0 0 0 7 data bits, 2 stop bits, even parity 0 0 1 7 data bits, 2 stop bits, odd parity 0 1 0 7 data bits, 1 stop bit, even parity 0 1 1 7 data bits, 1 stop bit, odd parity 1 0 0 8 data bits, 2 stop bits, no parity 1 0 1 8 data bits, 1 stop bit, no parity 1 1 0 8 data bits, 1 stop bit, even parity 1 1 1 8 data bits, 1 stop bit, odd parity

23. 6850 : Configuration - Interrupts Handshake and Interrupt Control: CR5 Transmit Control 1 CR6 Transmit Control 2 CR6 CR5 0 0 Set RTS = 0, Inhibit Transmit Interrupt 0 1 Set RTS = 0, Enable Transmit Interrupt 1 0 Set RTS = 1, Inhibit Transmit Interrupt 1 1 Set RTS = 0, Transmit “Break” and Inhibit Transmit Interrupt CR7 Receiver Interrupt Enable CR7 = 0 - Disable Interrupt in receive mode CR7 = 1 - Enable Interrupt in receive mode

24. Interrupts (1) There are two ways of telling when an I/O device is ready: 1. polling 2. interrupts An interrupt is a way of diverting the processor's attention away from its current program so that it may deal with some event that has occurred. change in state of a peripheral error from a peripheral Using interrupts means the processor does not have to continuously poll (check) the status of I/O devices.

25. Interrupts (2) In some processors, an interrupt is also known as a TRAP. In other cases TRAPs refer to system- generated interrupts for example: errors such as : division by 0, invalid opcode, access invalid memory address There are two types of interrupt • hardware • software A hardware interrupt may be thought of as a hardware-generated call to a special subroutine.

26. Interrupts (3) • The 68HC11 has three external, hardware interrupts. • 1. IRQ saves the state of the processor - loads the IRQ vector - executes the IRQ ISR - restores the state of the processor - orginal program in resumed. IRQ is maskable • 2. XIRQ high priority interrupt - non-maskable • 3. RESET - RESET line is held low for 8 cycles, loads RESET vector, computer restarts and previous CPU state is lost. RESET used on power-up or after catastrophic hardware or software failure non-maskable (highest priority). Some processors have special interrupts known as fast interrupts. (They are fast as they don’t save the cpu state, but leave that to the ISR writer’s discretion) • When a processor receives an interrupt, it: • saves it current state • loads address of routine to handle interrupt • executes Interrupt Service Routine (ISR) • Returns from interrupt (RTI instruction) and restores previous state • When processing an interrupt, the 68HC11 stores onto the stack: • program counter • Y index register • X index register • accumulator A • accumulator B • CCR • When returning from an interrupt, the 68HC11 reads back from the stack: • CCR • accumulator B • accumulator A • X index register • Y index register • program counter • The Interrupt Service Routine (ISR) is a subroutine specifically designed to handle a given interrupt. An ISR is run when the processor receives an interrupt. The CPU loads the vector corresponding to that interrupt that points to the appropriate ISR. • Each interrupt usually has a separate ISR associated with it. • An ISR will • determine the source of the interrupt • deal with event appropriately • Return from Interrupt (execute an RTI instruction) • Interrupts may be handled in two ways • interrupt polling: • - processor checks each device to determine which device generated the interrupt • - used when processor has limited number of interrupt lines • - used when I/O device has several sources of interrupt • vectored interrupts: • - each device corresponds to a single interrupt line and therefore a single vector or • - an I/O will supply the processor with a vector appropriate for the event that has occurred • The 68HC11 has one software interrupt (swi). • The software interrupt is used by programs to request services from the operating system. • eg: Print this character • Read a character • Read a string of characters • Read from the disk xxxx bytes of data to yyyy location • Check for network errors • Request for termination • How software interrupts are implemented depends on the operating system. • Some computers may only have a few calls supported. • Other processors may hundreds of different software interrupts and thousands of operating system calls supported. • When an operating system is requested via an SWI to perform a task for a program, it has to have some way of determining which task is needed. • This is accomplished using handles. A handle is a flag or indicator to the operating system indicating what is wanted. Each service available in the operating system has a handle associated with it. • Read a character from the keyboard, and print a character to the screen, and print a string of characters to the screen. • So decide to assign three handles: • 0 - Input a character from a keyboard • 1 - print a character to the screen • 2 - print a string of characters to the screen • Further decide that the handle will be assigned to the B accumulator. • Hence, whenever an operating system processes a software interrupt, it checks the B accumulator and with the number found there, it knows what service is required of the calling program. • Along with handles, such things as where the character to be printed is to be found where the input character is to be stored, are also defined. • Let us suppose that we use the A accumulator to hold the character in both of the above instances. • Then from application point of view, to read a character from the keyboard and then display it or screen, we have: • LDAB # 0 ; load handle for reading a character • SWI ; read in character, returns with character in accumulator A • LDAB # 1 ; load handle for printing a character • SWI ; print character • Now, if the B accumulator had an important value which we wanted to keep, we would naturally push it to the stack before we loaded the first handle, then pull it back whet have finished. • So the above program becomes: Now, if the B accumulator had an important value which we wanted to keep, we naturally push it to the stack before we loaded the first handle, then pull it back have finished. So the above program becomes: • PSHB ; save accumulator B to the stack • LDAB #0 ; load handler for reading a character • SWI ; get operating sys to read in character, returns with character in A • LDAB #1 ; load handle for printing character • SWI ; get operating system to print character in accumulator A • PULB ; pull accumulator B from the stack • Why use software interrupts? • Why use handles? • Operating systems and computers change with each new release. • Locations of I/O devices and operating system subroutines may be different in each new version. • The only thing that is constant is the location and function of the vector table. • The vectors in a computer will always correctly locate the appropriate routines. • By requesting the operating system via a software interrupt to perform system tasks for you, you avoid the possibility of your code not working on a new machine or operating system. • When processing an interrupt, the processor loads the vector associated with that interrupt. • The vector is the start address of the interrupt service routine (ISR) for that interrupt. • Vectors are located at a predefined location in the memory space. • For the 68HC11, the main vectors are: • Address Vector • FFF2..FFF3 IRQ (external) • FFF4..FFF5 XIRQ (external) • FFF6..FFF7 SWI (Software Interrupt) • FFF8..FFF9 Illegal opcode trap • FFFA..FFFB COP Failure • FFFC..FFFD Clock Monitor Fail • FFFE..FFFF RESET • The 68HC11 has many other vectors, but these are not relevant to the course. • Figure 3 Use of Priority Interrupt Controller to handle multiple interrupt sources • M68000 with Intel 8259 PIC.

27. Interrupts (4) When a processor receives an interrupt, it: completes its current instruction saves it current state loads address of routine to handle interrupt executes Interrupt Service Routine (ISR) Returns from interrupt (RTI instruction) and restores previous state

28. Interrupts (5) On interrupt, the 68HC11 saves on the stack: program counter Y index register X index register accumulator A accumulator B CCR Upon returning from an interrupt, the 68HC11 reads back from the stack: CCR accumulator B accumulator A X index register Y index register program counter

29. Interrupts (6) The Interrupt Service Routine (ISR) is a subroutine specifically designed to handle a given interrupt. An ISR is run when the processor receives an interrupt. The CPU loads the vector corresponding to that interrupt that points to the appropriate ISR. Each interrupt usually has a separate ISR associated with it. An ISR will then - determine the source of the interrupt - deal with event appropriately - Return from Interrupt (execute an RTI instruction)

30. Interrupts (7) Interrupts may be handled in two ways Interrupt polling: - ISR checks each device to find the device that generated the interrupt - used when processor has limited number of interrupt lines - used when I/O device has several sources of interrupt Vectored interrupts: - each device corresponds to a single interrupt line and therefore a single vector or - an I/O operation will supply the processor with a vector appropriate for the event that has occurred

31. Vectored Interrupts (1) Figure 3 Use of Priority Interrupt Controller to handle multiple interrupt sources M68000 with Intel 8259 PIC.

32. Software Interrupts (1) The 68HC11 has one software interrupt (swi). The software interrupt is used by programs to request services from the operating system. eg: Print this character Read a character Read a string of characters Read from the disk xxxx bytes to memory yyyy Check for network errors Request for termination How software interrupts are implemented depends on the operating system.

33. Software Interrupts (2) Some computers may only have a few calls supported. Other processors may hundreds of different software interrupts and thousands of operating system calls supported. When an operating system is requested via an SWI to perform a task for a program, it has to have some way of determining which task is needed. This is accomplished using handles. A handle is a flag or indicator to the operating system indicating what is wanted. Each service available in the operating system has a handle associated with it.

34. Software Interrupts (3) Read a character from the keyboard, and print a character to the screen, and print a string of characters to the screen. So we decide to assign three handles: 0 means Input a character from a keyboard 1 means print a character to the screen 2 means print a string of characters to the screen Further decide that the handle will be passed in the AccB. Hence, whenever an operating system processes a software interrupt, it checks the Acc. B and with the number found there, it knows what service is required of the calling program.

35. Software Interrupts (4) Along with handles, such things as where the character to be printed is to be found where the input character is to be stored, are also defined. Let us suppose that we use the A accumulator to hold the character in both of the above instances. Then from application point of view, to read a character from the keyboard and then display it or screen, we have: LDAB # 0 ; load handle for reading a character SWI ; read in character, returns with ; character in accumulator A LDAB # 1 ; load handle for printing a character SWI ; print character

36. Software Interrupts (5) Now, if the B accumulator had an important value which we wanted to keep, we would naturally push it to the stack before we loaded the first handle, then pull it back whet have finished. So the above program becomes: PSHB ; save accumulator B to the stack LDAB #0 ; load handler for reading a character SWI ; get operating sys to read into AccA LDAB #1 ; load handle for printing character SWI ; get operating system to print char PULB ; pull accumulator B from the stack

37. Software Interrupts (6) Why use software interrupts? Why use handles? Operating systems and computers change with each new release. Locations of I/O devices and operating system subroutines may be different in each new version. The only thing that is constant is the location and function of the vector table. The vectors in a computer will always correctly locate the appropriate routines. By requesting the operating system function via a software interrupt, you avoid the possibility of your code not working on a new machine or operating system.

38. Software Interrupts (7) When processing an interrupt, the processor loads the vector associated with that interrupt. The vector is the start address of the interrupt service routine (ISR) for that interrupt. Vectors are located at a predefined location in the memory space. (Buffalo uses well-defined jump table locations for access to I/O routines. SWI is used to call Buffalo)

39. Interrupt Vector Table • For the 68HC11, the main vectors are: • Address Vector • FFF2..FFF3 IRQ (external) • FFF4..FFF5 XIRQ (external) • FFF6..FFF7 SWI (Software Interrupt) • FFF8..FFF9 Illegal opcode trap • FFFA..FFFB COP Failure • FFFC..FFFD Clock Monitor Fail • FFFE..FFFF RESET • The 68HC11 has many other vectors, but these are not relevant to the course.

40. Example simple ISR • LDX BUF_HEAD ; Get the buffer pointer • LDAA $7000 ; load character from ACIA • STAA 0, X ; store character in buffer • INX ; point to next byte in buffer • CPX BUF_END ; is (X > end of buffer), then • BLO NO_WRAP ; circular buffer - wrap to start • LDX BUF_START ; • NO_WRAP: • STX BUF_HEAD ; save the pointer back • RTI ; & return from interrupt • BUF_HEAD RMB 2 • BUF_START EQU 7FF0 • BUF_END EQU 7FFF

41. ISR cycle timing • Instruction Completion ; 9 • Interrupt Entry ; 14 • LDX BUF_HEAD ; 3 • LDAA $7000 ; 2 • STAA 0, X ; 4 • INX ; 1 • CPX BUF_END ; 4 • BLO NO_WRAP ; 3 • LDX BUF_START ; 3 • NO_WRAP: • STX BUF_HEAD ; 4 • RTI ; 12 • 59 cycles (minimum) * 0.5us = ISR time = 29us • What is this maximum data reception rate? • 33898 interrupts / second, best case on 2MHz 68HC11.

42. Serial communications 16550 UART Configuration

43. Serial communications 16550 UART Configuration At IO Address COM1 3F8..3FF, COM2 2F8..2FF, COM3 3E8..3EF, COM4 2F8..2FF

45. Serial communications Interrupt Enable Register (IER) The IER enables each of the five types of interrupts and enables INTRPT in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents of this register are summarised in the previous table

46. Serial communications Interrupt Identification Register (IIR) P1 The ACE has an on-chip interrupt generation and prioritization capability. The ACE provides four prioritized levels of interrupts: Priority 1 - Receiver line status (highest priority) Priority 2 - Receiver data ready/receiver character time-out Priority 3 - Transmitter holding register empty Priority 4 - Modem status (lowest priority) When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of interrupt in its three least significant bits (bits 0, 1, and 2).

47. Serial communications Interrupt Identification Register (IIR) P2 Detail on each bit is as follows: Bit 0: When bit 0 is cleared, an interrupt is pending Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in the previous table. Bit 3: This bit is always cleared in 16C450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that a time-out interrupt is pending. Bits 4 and 5: not used (always cleared). Bits 6 and 7: These bits are always cleared in 16C450 mode. They are set when bit 0 of the FIFO control register is set.

48. Serial communications Line Control Register (LCR) In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates the need for separate storage of the line characteristics in system memory. Bits 0 and 1: Number of bits in each serial character. 00=5 bits, 01=6 bits, 10=7 bits, 11=8 bits Bit 2: Specifies either 1, 1.5 or 2 stop bits If Bit 3=: parity bit is generated in transmitted data between the last data word bit and the first stop bit. In received data parity is checked. If Bit 3=0: no parity is generated or checked.

49. Serial communications Line Control Register (LCR) When parity is enabled and: Bit 4=1 Even Parity - An even number of logic 1s in the data and parity bits is selected. Bit4=0 odd parity - An odd number of logic 1s is selected. Bit 5=1 Stick Parity. The parity bit set to 0. Bit 5=0 Stick parity is disabled.

50. Serial communications Line Control Register (LCR) Bit 6: Break control bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT is forced to the spacing (cleared) state. Bit 7: Divisor Latch Access Bit (DLAB). Bit 7 must be set to access the divisor latches of the baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver buffer, the THR, or the IER.