EEL 3705 / 3705L Digital Logic Design

1. EEL 3705 / 3705LDigital Logic Design Fall 2006Instructor: Dr. Michael FrankModule #8: Modular Combinational Logic(Thanks to Dr. Perry for some slides) M. Frank, EEL3705 Digital Logic, Fall 2006

2. Wednesday, Jan. 31, 2007 • Announcements: • “Perfect Lab #1 Report” example has been posted • go over it • You are doing your Lab #2s this week • Lab #3 assignment will be posted later today • Modular 2-digit display, reusing 1-digit circuit • HW#1 will be posted tonight or tomorrow • Midterm #1 tentatively scheduled for Feb. 12th • Today’s lecture material: • How to group wires in simulator and count through input values • Introduction to modular combinational design M. Frank, EEL3705 Digital Logic, Fall 2006

3. Upcoming Schedule M. Frank, EEL3705 Digital Logic, Fall 2006

4. Monday, Feb. 5, 2007 • Announcements: • Midterm #1 will be 1 week from today • We will have a review session in class this Friday. • A homework assignment (for the lecture course) has been posted on Blackboard • It is to help prepare you for the midterm exam • It is due midnight this Wednesday • Lab #3 is starting Tuesday • Come to my office hours Tu. 2-5 pm if you are stuck! • Today’s Topic: • Continue coverage of common modular components: • Decoders, encoders, multiplexers, demultiplexers… M. Frank, EEL3705 Digital Logic, Fall 2006

5. Midterm Exam Coverage Midterm Exam #1 will cover the following CIOs: • CIO #1. [BinConv] Convert numbers between different number systems (including binary, octal, decimal and hexadecimal). • CIO #3. [BoolCirc] Derive digital circuits from optimized Boolean equations and compute the Boolean equations of a digital circuit. • CIO #5. [K-maps] Use Karnaugh maps to optimize combinational logic, including incompletely specified logic. M. Frank, EEL3705 Digital Logic, Fall 2006

6. Upcoming schedule M. Frank, EEL3705 Digital Logic, Fall 2006

7. Why K-maps are Rarely Used In Practice • In the real world, combinational functions of significant complexity (more than n=4 or so input bits) are almost never designed as flat, 2-level Sum-of-Products expressions optimized via K-maps. • Some of the reasons are: • The truth tables become large and unweildy (2n rows) • Groupings can’t be easily seen on multi-chart K-maps • Circuit structure becomes large, complex and error-prone • In some cases, even minimal sum-of-products circuits may be exponentially larger (& slower) than alternative designs! • Designers would be constantly “reinventing the wheel” M. Frank, EEL3705 Digital Logic, Fall 2006

8. Modular Combinational Design • Rather than using flat AND-OR functions, the preferred, more practical design methodology for any complex combinational component is modular design. • The idea is to create and use libraries of commonly-encountered, reusable modular components, use them as building blocks… • And compose larger, more complex functions out of them. • In a lot of ways, this type of activity has a flavor very similar to software engineering! • This methodology is vastly more efficient in terms of design time, debugging, and understandability and ease of modification of designs. • The resulting designs may not be the most optimal possible, but flat AND-OR designs in many cases would be even less optimal, and would be much harder to maintain! M. Frank, EEL3705 Digital Logic, Fall 2006

9. The following common elements have a wide variety of uses: Code conversion, arbitrary functions, etc.: Decoders Encoders Priority encoders Selection & routing of data: Multiplexers Demultiplexers Lookup tables for arbitrary functions: ROMs Integer arith. elements: Half adders Full adders n-bit adders Ripple-carry adder Negaters Subtracters Comparators Absolute-value Multiplers (tend to be slow) Dividers (tend to be slow) Floating-point arithmetic elements Slower, often sequential Some Commonly Encountered Modular Combinational Components M. Frank, EEL3705 Digital Logic, Fall 2006

10. Decoders • General form: k-to-2k decoder • Input: A k-bit wide bus encoding a binary number n:nk−1nk−2 … n2 n1 n0 • Output:K=2k bits, e0 … eK−1 • Where ei = 1 if and only if n=i • I.e., the propositional meaning of ei is “n is equal to i” • ei thus also corresponds to the ith minterm mi of the input literals e0 e1 e2 e3 n … k eK-1 When the input is i,output ei = 1, and allother outputs are 0. We could also drawthe output as a bus of K=2k wires. M. Frank, EEL3705 Digital Logic, Fall 2006

11. 2 to 4 Decoder – Truth Table & Boolean Equations M. Frank, EEL3705 Digital Logic, Fall 2006

12. Some Common Uses of Decoders • Selecting a designated device to activate • Accessing rows/columns of a memory array • Generating minterms to combine with OR gates to implement some arbitrary function • Code conversion (with an encoder) M. Frank, EEL3705 Digital Logic, Fall 2006

13. Example of Using a Decoder to Compute an Arbitrary Function • This is a decimal 7-segment driver • Like you did for lab 2, but not using K-maps We could further simplifyby deleting the “eq8” output,which isn’t used. Note that the minterms for digit values 0-9can be shared among all the sum-of-minterms functions that use them, and notrecomputed for each one. M. Frank, EEL3705 Digital Logic, Fall 2006

14. Encoders • Draw an example 8-to-3 encoder on the board. • Show how to use together with a decoder for code conversion. M. Frank, EEL3705 Digital Logic, Fall 2006

15. Example Encoder Implementation • Any simple encoder can be built just with OR gates… Here’s an 8-to-3 encoder. M. Frank, EEL3705 Digital Logic, Fall 2006

16. Brief aside: Gray codes • To illustrate code conversion, let’s consider an alternative 3-bit binary code for the numbers 0-7. • This one isn’t a radix code! • I.e. individual “bit positions” don’t have values that can be added up to give the value of the number • Instead of the ordinary unsigned base-2 radix expansion of the number, we’ll use a Gray code. • This is a code in which the bit patterns for successive numbers differ in only 1 bit position • We used them already for labeling rows and columns of K-maps; they are also useful for labeling regions of storage media. • A Gray code {gi} for a number can be generated from that number’s radix code {ri} by letting each bit gi of the gray code be given by gi = ri+1ri. • A table of the Gray code generated in this way for 3-bit numbers is shown at right. M. Frank, EEL3705 Digital Logic, Fall 2006

17. Example of Using an Encoder-Decoder Pair to do Code Conversion • 3-bit Binary to Gray-code converter Between the decoder and encoder, all we need to implement the mapping are wires, connected appropriately! M. Frank, EEL3705 Digital Logic, Fall 2006

18. Wed. 2/7/07 • Lab 3 this week • HW1 due tonight @ midnight • Sample exam to be posted • Go over solutions Friday • Midterm on Monday • Lab practicals next week M. Frank, EEL3705 Digital Logic, Fall 2006

19. A Simpler Design • Of course, in this case, there is a much simpler implementation of this particular code converter that is based directly on the mathematical definition of the Gray code bits: • This illustrates the general point that it is usually simpler to implement a given non-random function in terms of its mathematical definition, rather than using generic methods. • But, you should still be aware that, if necessary, any arbitrary binary code (even one with a random structure) could be translated to any other using a decoder/encoder pair. • But the method is not very practical for large codeword sizes. M. Frank, EEL3705 Digital Logic, Fall 2006

20. Multiplexers (Muxes, Selectors) • A multiplexer selects one of several data input signals to pass through to its output. • It is analogous to a switch/case statement in C. • A multiplexer is defined as follows: • There is an n-bit-wide “select” or “control” input, call it s = sn−1..0. • It is a radix-2 encoding of the index number of the data input line to be selected. • There are N ≤ 2n data input lines, call them d0..dN−1 • All the same width as each other – here 1 bit • They are the alternatives we are selecting among • There is one output line, q = ds. • The output is equal to the selected input. d0 d1 … q dN−1 sn−1..0 n M. Frank, EEL3705 Digital Logic, Fall 2006

21. Building a 4-to-1 Mux from a Decoder M. Frank, EEL3705 Digital Logic, Fall 2006

22. Building an Arbitrary Boolean Function (BCD-to-7segment Decoder) Using a MUX M. Frank, EEL3705 Digital Logic, Fall 2006

23. Note to Self • There are still way too many slides in the rest of this module! • Need to keep working on making it shorter and more concise M. Frank, EEL3705 Digital Logic, Fall 2006

24. Modular Combinational Logic Original slides by Dr. Reginald Perry With modifications & additions by Mike Frank M. Frank, EEL3705 Digital Logic, Fall 2006

25. Decoders • General form: n-to-2n decoder • n inputs, 2n outputs • For each input pattern, one and only one output line will be active. • Uses: • “Minterm generator” • Bit/word-line (memory access) circuit • Code conversion • Demultiplexing (routing) of data M. Frank, EEL3705 Digital Logic, Fall 2006

26. 1-to-2 Decoder • Truth table shown at right • This one can be implementedby just a simple fan-out andan inverter: y0 y0 x x y1 y1 Circuit schematic Icon M. Frank, EEL3705 Digital Logic, Fall 2006

27. Recursive Contruction of n-to-2n Decoder out of 1-to-2 and (n−1)-to-2n−1 Decoders w0 …plus 2n AND gates w1 w2 xn−1..1 xn−1..0 2n−1 ANDgates 2n−1 … n−1 2n 2n−1 ANDgates z0 x0 z1 M. Frank, EEL3705 Digital Logic, Fall 2006

28. 1-to-2, 2-to-4 and 3-to-8 Decodersusing recursive design style in Quartus This is really 4 AND gates in parallel This is really 8 AND gates in parallel M. Frank, EEL3705 Digital Logic, Fall 2006

29. add a slide on the other recursive composition of 2k-to-(2^(2k)) decoders M. Frank, EEL3705 Digital Logic, Fall 2006

30. 2 to 4 Decoder Equations M. Frank, EEL3705 Digital Logic, Fall 2006

31. 2 to 4 Decoder: Circuit M. Frank, EEL3705 Digital Logic, Fall 2006

32. 2 to 4 Decoder: Block Symbol Symbol Circuit M. Frank, EEL3705 Digital Logic, Fall 2006

33. 3 to 8 Decoder – Truth Table M. Frank, EEL3705 Digital Logic, Fall 2006

34. 3 to 8 Decoder Equations M. Frank, EEL3705 Digital Logic, Fall 2006

35. 3 to 8 Decoder: Circuit M. Frank, EEL3705 Digital Logic, Fall 2006

36. 3 to 8 Decoder: Block Symbol Symbol Circuit M. Frank, EEL3705 Digital Logic, Fall 2006

37. Design Example • Using only a 3x8 decoder and two-input OR gates, design a logic circuit which implements the following Boolean equation M. Frank, EEL3705 Digital Logic, Fall 2006

38. Solution m2 m4 m5 M. Frank, EEL3705 Digital Logic, Fall 2006

39. 2 to 4 Decoder with Enable M. Frank, EEL3705 Digital Logic, Fall 2006

40. 2x4 Decoder with Enable • Enable is abbreviated as EN • EN is called a Control Signal • Control Signals can be • Active High Signal • EN = 1 – Turns “ON” Decoder • Active Low Signal • EN=0 – Turns “ON” Decoder M. Frank, EEL3705 Digital Logic, Fall 2006

41. 2 x 4 Decoder with Active High Enable – Truth Table M. Frank, EEL3705 Digital Logic, Fall 2006

42. 2 to 4 Decoder with Enable Equations M. Frank, EEL3705 Digital Logic, Fall 2006

43. 2 to 4 Decoder with Enable Circuit M. Frank, EEL3705 Digital Logic, Fall 2006

44. 2 to 4 Decoder with Enable Symbol M. Frank, EEL3705 Digital Logic, Fall 2006

45. 2 x 4 Decoder with Active High Enable – Truth Table (Short hand notation) d = don’t care En has “highest” priority. If En=0, we “don’t care” about x1 or x0 because Y=0 M. Frank, EEL3705 Digital Logic, Fall 2006

46. 2 x 4 Decoder with Active Low Enable – Truth Table (Short hand notation) d = don’t care En has “highest” priority. If En=1, we “don’t care” about x1 or x0 because Y=0 M. Frank, EEL3705 Digital Logic, Fall 2006

47. 2 to 4 Decoder with Active Low Enable Circuit M. Frank, EEL3705 Digital Logic, Fall 2006

48. Design Example • Design a 3x8 decoder using only 2x4 decoders and NOT gates. M. Frank, EEL3705 Digital Logic, Fall 2006

49. Solution “On” when A=0 “On” when A=1 M. Frank, EEL3705 Digital Logic, Fall 2006

50. Encoders • Opposite of a decoder • 2n to n encoder • 2n inputs • n outputs • For each input, the circuit will produce an “encoded” output M. Frank, EEL3705 Digital Logic, Fall 2006