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Poster

Smart FPGA Based SAT Solver. Saleem Sabbagh & Najeeb Darawshy Supervisors: Mony Orbach, Technion & Ilia Averbouch, IBM. Poster. Started at: Spring 2012 Duration: Semester. Abstract.

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Poster

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  1. Smart FPGA Based SAT Solver Saleem Sabbagh & Najeeb Darawshy Supervisors: Mony Orbach, Technion & Ilia Averbouch, IBM Poster Started at: Spring 2012 Duration: Semester

  2. Abstract After the conclusion of our previous project, in which we have developed a platform to implement SAT instances onto an FPGA device, along with a random SAT solver, we embarked on building a smarter platform that enables us to significantly cut down compilation times and more importantly to reduce the time it takes to find the satisfying assignment of a given SAT (runtimes). the schemes we have implemented to meet our goals were: • Building a sophisticated SAT solver GSAT • Implementing an application specific SAT solver using the memory of the FPGA device.

  3. What is sat • Boolean Satisfiability Problem • Given a Boolean propositional formula, does there exist assignment of values such that the formula becomes true? • e.g., given the formula f=(x1 ˅ x3˅ -x4) ˄ (x4) ˄ (x2 ˅ -x3) are there values of x1,x2,x3,x4 that produce f=‘1’ • Satisfiabilitysolvers are increasingly leaving their mark as a general-purpose tool in areas as diverse as software and hardware verification, automatic test pattern generation, planning, scheduling, and even challenging problems from algebra by solving SAT instances made by transforming problems that arise in those areas.

  4. Specification • Software: • We have developed a SAT Parser which will convert the input SAT instance from a known DIMACS format to a memory initialization file MIF format. • Altera Quartus II for connecting to the board via JTAG. • Hardware: • Altera DE2 Board with Altera Cyclone® II 2C35 FPGA device for implementing SAT instance and running GSAT SAT solver.

  5. Flow diagram Reset Convert PC In System Memory Content Editor SignalTap DE2

  6. Controller attempts == allowed • Init • Reset circuit • Random Assignment • Clauses Init • Var by var run and save to shiftreg • Flipping • Flip variable value • Sum satisfied clauses • Advance var var == total vars var == total vars • Finish • Output satisfying assignment • Maximum • Increase attempts if max <= 0 • Flip max var and save to shiftreg satisfied == total clauses attempts == allowed

  7. BLOCKdiagram

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