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Regular Expression Acceleration at Multiple Tens of Gb/s

Regular Expression Acceleration at Multiple Tens of Gb/s. Author: Jan van Lunteren , Jon Rohrer, Kubilay Atasu , Christoph Hagleitner Publisher: ICS,2009 Presenter: Jia-Wei,You Date : 2012/5/2. Introduction.

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Regular Expression Acceleration at Multiple Tens of Gb/s

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  1. Regular Expression Acceleration at Multiple Tens of Gb/s Author: Jan van Lunteren, Jon Rohrer, KubilayAtasu, ChristophHagleitner Publisher: ICS,2009 Presenter:Jia-Wei,You Date:2012/5/2

  2. Introduction • Our approach is based on a novel type of programmable state machine in hardware, called BaRT-based Finite State Machine (B-FSM) • The key focus is on improving the storage efficiency.

  3. Transition Rules

  4. Transition Rule Table • a hash index is derived by the address generator from the current state and input value based on the mask stored in the mask register according to (1). • Transition rules involving a wildcard condition for the current state, such as rules R0 and R1 in Fig. 1(b), will be handled differently for storage-efficiency reasons, and are stored in the so-called “default rule table”.

  5. Transition Rule Selection Current state: S0 : 00h , S1 : 02h , S2 : 01h S3 : 10h , S4 :04h Mask: S2(0000010b) S3(0010000b) S1 and S4(0000000b)

  6. B-FSM

  7. Pattern matching engine

  8. Experimental result

  9. Performance • Xilinx Virtex-4 • B-FSM implementation based on six Block RAMsproviding a total storage capacity of about 13 KB : four Block RAMs (9 KB) were used for the transition-rule memory, one Block RAM for a combined implementation of the (ASCII-based) character classifier and the default rule table. • 16 B-FSMs ran at 125MHz, consuming 33% of available Block RAM. • 1Gb/s for each B-FSM.

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