RE al TI me S ystems Lab

1. 2005 Giuseppe Lipari REal TIme Systems Lab

2. The RETIS lab at Scuola Superiore Sant’Anna Mission Advance the state of the art in Real-Time Systems Technology Apply RTST to real-world applications Spread knowledge on RTST Staff: Director: Marco Di Natale (Ass. Professor) • 2 full professors • 2 associate professors • 3 assistant professors • 7 PhD students • 2 research collaborators • 1 administrative Contact Info: Web: http://retis.sssup.it Tel: +39 050 882 002 Fax: +39 050 882003

3. The RETIS Lab: A (very) quick tour Applications Technologies Automotive systems: Janus Next Generation RTOS kernels for multiprocessor (etherogeneous) systems-on-chip DEMO Sensor Networks Algorithms for analysis and synthesis of embedded systems designs Adaptive multimedia scheduling DEMO (Improvements to) Real-time Linux Emb. systems design tools Resource-reservation based scheduling Algorithms for adaptive scheduling DEMO DEMO HW (FPGA) implementation of real-time kernel structures Smart card fingerprint matching Power management dynamic HW (FPGA) reconfiguration for implementation of real-time tasks Smart card implementation of multimodal fingerprint matching and security middleware

4. The RETIS Lab: 5th FP and Nat.l Projects Improving RT-Linux QoS management in Linux Power management Next Generation RTOS Component Based Flexible RT Systems FABRIC Federated Applications based on Real-Time Interacting Components Network of excellence on Real-Time systems To coordinate the research on RT at the EU level PISATEL Collaboration with Ericsson and CNR (IEI) Quality of Service in component-based embedded systems Real-Time embedded control systems Financing: • 5 EU IST projects • 2 MIUR projects • 2 Italian projects • 1 Private (industry) funding

5. RTOS for Embedded Systems PARADES • Research on: • New scheduling strategies for embedded multi-processor systems • homogeneous (dual or n-CPU) or etherogeneous (CPU + DSP) • Scheduling with offsets • Modular and portable RT kernel, with minimal memory footprint • Application: • Automotive industry • Embedded systems in general E.R.I.K.A. http://erika.sssup.it In collaboration with

6. Automotive electronics The use of electronics in cars is increasing Engine control Stability control Critical real-time software! • Janus system-on-a-chip (SoC) for automotive applications • developed by ST, Magneti Marelli, Parades GEIE • multiprocessor architecture (dual ARM) • high performance • low cost

7. The Janus Chip Jointly developed by ST, MM, Parades system on-chip architecture (SoC) Symmetric bi-processor (2 ARM7TDMI) High performance bus specialized I/O for engine control Features • 11% additional silicon area with respect to single-ARM solution • 2x computing power • Fits the requirements of next generation engine control systems

8. The Janus Chip Memory in Janus (and other SoCs) large amount of Flash (512 Kb) limited amount of RAM (16 Kb) RAM memory costs in terms of chip space ! Sample die of a speech-processing chip Sample SoC (speech process. chip for security apps) picture • 68HC11 micro • 12Kb ROM • 512 bytes RAM in approx. the same space (24x cost!)

9. Janus and Erika high performance Small footprint (less than 1K (ST10) 1.8K (ARM) ) Fast execution time (ctx < 10µs (ST10) 4.2µs (ARM)) minimal RAM requirements Stack sharing using preemption thresholds and one shot task model Optimization algorithms and tools available Innovative guaranteed Real-Time Scheduling EDF and Fixed Priority (FP) schedulers Communication primitives with limited blocking time Resource sharing with limited blocking time (SRPT) multiprocessor resource sharing (mutex) Multiprocessor implementation of EDF and SRPT (MSRPT)

10. Erika and multiprocessors OSEK/VDX is not ready to cope with the challenges posed by a multiprocessor system. innovative mechanisms that allow exploiting the main features of OSEK's immediate priority ceiling in multiprocessor systems; tools that support thread placement on processors The Multiprocessor hiding concept Seamlessly migrate application code from a single processor to multiprocessors without changing the source code. Only requires (limited) OIL extensions industries can maintaining their code base, being able to target an application to single and multiprocessor architectures at the same time by using different OIL configurations, but same source code.

11. RTOS support for reconfigurable HW • Research objectives: • Porting erika on reconfigurable devices • support for deep parallelism • Supporting dynamic offloading of SW tasks onto HW • improving the performance of critical real-time tasks • requires integrated scheduling wrt (real) time constraints and space constraints (FPGA available elements) • Specialized HW implementation of kernel structures • HW support for real-time (EDF) scheduling, multiprocessor communication and distributd communication • FPGA target: an example • Altera’s low-cost Cyclone II FPGA family • 4,480 to 68,288 logic elements (LEs) and up to 1.1 Mbits of embedded RAM. • Up to 250-MHz operation • Nios II processor • general-purpose RISC processor core • 32-bit instruction set, data path, and address • +200 DMIPS performance in ~1,800 LEs • $0.35 of logic.

12. Resource Reservation and Soft RT systems Research on: Soft real-time scheduling strategies Resource Management in RT systems QoS management RT Linux Objective: Support QoS requirements in general purpose operating systems Modify the Linux kernel to support real-time multimedia application Teleconference Video streaming A middleware architecture for QoS Supported by OCERA IST project

13. Flexible scheduling Elastic scheduling Hierarchical scheduling Mixing hard and scheduling Adaptive scheduling using control theory to perform adaptive scheduling and provide adequate bandwidth to multimedia applications Supported by FIRST IST project

14. Design of Embedded Systems Performance of control applications: Performance analysis of RT control applications Simulation of control applications Analysis and Synthesis of task architecture parameters optimization of application performance with schedulability constraints sensitivity analysis RT-UML Profile for the HRT-Hood methodology Supported by RECSYS IST project

15. Power aware scheduling Modification of the Linux scheduler Measures system load Decreases the clock frequency in case of low load Respects Quality of Service requirements Implemented on Intel Xscale processor Saves up to 50% of energy Distributed under GPL

16. OS/MW software for sensor networks Real-Time scheduling changing scheduling policies of TinyOS/ porting Erika Support for real-time messages System-level power management handling CPU scheduling, sensor and RF transmitter operations • Middleware • energy-aware routing with QoS guarantees

17. Security and smartcards Design and Implementation of software emulator for smarcard applications Evaluation of protocol interoperability for smarcards Biometric technologies for multimodal authentication using smartcards Middleware for supporting etherogeneous protocols and smartcards for system security and authentication Open-Source Software

18. RETIS Lab. and the International research community International Master on Information Technology Joint initiative of the Scuola Superiore Sant’Anna and the Indo-Italian Chamber of Commerce and Industry Financed by MIUR and Ministero degli Esteri International school on real-time operating systems ARTIST Network of Excellence Strong participation to the most relevant conferences 11 papers in the last four years at RTSS (out of about 130 accepted, overall accept. ratio about 25%) participating to technical and/or program committees at RTSS, RTAS, DAC, Euromicro RTS) Cooperation with international labs (visiting PhDs) Carnegie Mellon Univ., Univ. California at Berkeley, Univ. Of North Carolina at Chapel Hill, Univ.of Illinois, Univ. of Massachusetts ...

19. That’s all folks ! • Please ask your questions or look at our demos ...