COMP2121: Microprocessors and Interfacing

1. COMP2121: Microprocessors and Interfacing Instruction Formats and Addressing Modes http://www.cse.unsw.edu.au/~cs2121 Lecturer: Hui Wu Session 2, 2007

2. Overview • Instruction format • AVR instruction format examples • PowerPC instruction format examples • Addressing Modes • AVR Instruction Examples

3. Instruction Formats • Instructions typically consist of • Opcode (Operation code) – defines the operation (e.g. addition) • Operands – what’s being operated on (e.g. particular registers or memory address) • There are many different formats for instructions

4. Instruction Formats OpCode OpCode Opd OpCode Opd1 Opd2 OpCode Opd1 Opd2 Opd3 • Instructions typically have 0, 1, 2 or 3 operands • – Could be memory addresses, constants, register addresses (i.e. register numbers)

5. AVR Instruction Examples • Clear register. • Syntax: clr Rd • Operand: 0  d  31 • Operation: Rd ← 0 • Instruction format. 0 0 1 0 0 1 d d d d d d d d d d 0 15 – OpCode uses 6 bits (bit 9 to bit 15). – The only operand uses the remaining 10 bits (only 5 bits (bit 0 to bit 4) are actually needed).

6. AVR Instruction Examples • Subtraction with carry. • Syntax: sbc Rd, Rr • Operation: Rd ← Rd – Rr – C • Rd: Destination register. 0  d  31 • Rr: Source register. 0  r  31 C: Carry • Instruction format. 0 0 0 0 1 0 r d d d d d r r r r 0 15 – OpCode uses 6 bits (bit 9 to bit 15). – Two operands share the remaining 10 bits.

7. Instruction Lengths • On some machines – instructions are all the same length • On other machines – instructions can have different lengths

8. AVR Instruction Examples • Almost all instructions are 16 bits long. • – add Rd, Rr • – sub Rd, Rr • – mul Rd, Rr • – brge k • Few instructions are 32 bits long. • – lds Rd, k ( 0  k  65535 ) • loads 1 byte from the SRAM to a register.

9. Design Criteria for Instruction Formats • 1. Backwards Compatibility • e.g. Pentium 4 supports various instruction lengths so as to be compatible with 8086 2. Instruction Length • Ideally (if you’re starting from scratch) • All instructions same length • Short instructions are better (less memory needed to store programs and can read instructions in from memory faster)

10. Instruction Design Criteria (cont.) 3. Room to express operations • 2n operations needs at least n bits • Wise to allow room to add additional opcodes for next generation of CPU 4. Number of operand bits in instruction • Do you address bytes or words?

11. OpCode  Operand Tradeoffs • Instructions can tradeoff number of OpCode bits against number of operand bits • Example: • 16 bit instructions • 16 registers (i.e. 4-bit register addresses) • Instructions could be formatted like this: • But what if we need more instructions and some instructions only operate on 0, 1 or 2 registers? OpCode Operand1 Operand2 Operand3

12. Expanding OpCodes • Some OpCodes can mean “look elsewhere in the instruction for the real OpCode” • e.g. if first 4 bits are 1111, OpCode is really contained in next 4 bits (i.e. effectively an 8 bit OpCode), and so on

13. Expanding OpCodes • Other combinations are possible • Exercise (two minutes) For a 16 bit instruction machine with 16 registers, design OpCodes that allow for • 14 3-operand instructions • 30 2-operand instructions • 30 1-operand instructions • 32 0-operand instructions

14. 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 1 0 PowerPC Examples • PowerPC ISA defines OpCode as the first six bits • This specifies type of instruction (operation) • OpCode specifies format of the rest of the instruction

15. 32 bits 6 bits 5 bits 5 bits 16 bits 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value (2’s complement) OpCode Source Register Destination Register PowerPC Machine Instruction Example1 • OpCode (001110two or 14) tells us that this instruction is an integer addition: destination-register = source-register + value r5 = r12 + (-1)

16. 6 bits 11 bits 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 1 0 OpCode Secondary OpCode PowerPC Machine Instruction Example2 • OpCode (111111two or 63) tells us this is a double precision floating point instruction • But it does not tell us what it actually does! • We need to look at a Secondary OpCode

17. 5 bits 5 bits 5 bits 1 1 1 1 1 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 1 0 Destination Register Source Registers A & B PowerPC Machine Instruction Example 2 Secondary OpCode • Secondary OpCode (42) tells us this is a double precision floating point addition destination-reg = register-A + register-B fr13 = fr26 + fr6

18. Operands • Instructions need to specify where to get operands from • Some possibilities • Value is in instruction • Value is in a register • Register number is in the instruction • Value is in memory • address is in instruction • address is in a register • register number is in the instruction • address is register value plus some offset • register number is in the instruction • offset is in the instruction (or in a register) • These are called addressing modes

19. Immediate Addressing • Not really an addressing mode – since there is no address • Instruction doesn’t have address of operand – it has the value itself • i.e. the operand is immediately available • Limits to the size of the operand you can fit in an instruction (especially in RISC machines which have instruction word size = data word size)

20. Immediate Addressing Examples • AVR • Pentium SUBI ADIW mov ebx, KKKK

21. Direct Addressing • Address of the memory operand is in the instruction • Useful for global variables (accessible from all subroutines) • AVR Datasheet calls this “Data Direct Addressing” and I/O Direct Addressing.

22. Direct Addressing Examples • AVR STS • Pentium mov eax,[kk]

23. Register Direct Addressing • Register numbers are contained in the instruction • Data in the registers. • Fastest mode and most common mode in RISC • Example: ADD AVR Pentium Sparc

24. Register Indirect Addressing • Register number in instruction, as with register addressing • However, contents of the register is used to address memory • the register is used as a pointer • AVR datasheet calls this “Data Indirect” addressing

25. Register Indirect Addressing Example • AVR • LDD Rd, Y Operation: Rd(Y) Y: r29: r28

26. Indexed Addressing • Reference memory at a known offset from a register • Two main uses: • Register holds address of object; fixed offset indexes into the object (structure, array, etc) • Address of object is constant; register has index into the object • AVR datasheet calls this “Data Indirect with Displacement” addressing (fixed offset, not in register)

27. Indexed Addressing Examples • AVR (data indirect with displacement) • Only 6 bit displacement (q bits) • Only Y or Z index registers • determined by this bit • Operation: Rd  (Y + q) LDD Rd, Y+q

28. Auto Increment • Some architectures allow modification of the index register as a side effect of the addressing mode • Usually add or subtract a small constant, often equal to the operand size • Could happen before or after the index register is used in the address calculation • Most common are post increment and pre decrement • AVR supports these • “Data Indirect with Pre-decrement” • “Data Indrect with Post-increment”

29. Auto Increment Examples • AVR • LDD Rd, -Y Operation: Y  Y–1 Rd  (Y) LDD Rd, Y+ Operation: Rd  (Y) Y  Y+1

30. Code Memory Constant Addressing • AVR has separate data and instruction memories • Sometimes need to get data constants out of instruction memory (flash memory) • Special instruction provided to do this (LPM) • LPM Rd, Z Operation: Rd  (Z) Load a byte at the address contained in register Z (r30: r29)

31. Branch Instructions • Specify where in the program to go next (i.e. change the program counter rather than just increment) • program flow is no longer linear • Types of Branch Instructions • Unconditional – always do it • Conditional – do it if some condition is satisfied (e.g. check status register) • Jumps – no return • Subroutines (function calls) – can return

32. Branch Instruction Addressing Modes • Direct addressing • Address to jump to included in the instruction • Not every AVR device support this (JMP and CALL instructions) • Indirect addressing • Address to jump to is in a register • AVR examples: IJMP, ICALL • Program Counter Relative addressing • AVR calls this “Relative Program Memory” addressing • Add a constant value to the Program Counter • AVR examples: RJMP, RCALL, conditional branch instructions…

33. Branch Instruction Addressing Modes: AVR Examples • JMP k • Operation: PC  k (0 k  4M) • IJMP • Operation: PC  Z

34. Branch Instruction Addressing Modes: AVR Examples • BRGE k (signed) • Operation: If Rd  Rr then PC  PC+k+1 else PC  PC+1 • Operand: -64  k  +63

35. Reading Material • Chapter 4 in Microcontrollers and Microcomputers.