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Control Units

Control Units. Discussion D8.3 Example 38. Integer Square Root. unsigned long sqrt(unsigned long a){ unsigned long square = 1; unsigned long delta = 3; while(square <= a){ square += delta; delta += 2; } return (delta/2 - 1); }. Integer Square Root.

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Control Units

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  1. Control Units Discussion D8.3 Example 38

  2. Integer Square Root unsigned long sqrt(unsigned long a){ unsigned long square = 1; unsigned long delta = 3; while(square <= a){ square += delta; delta += 2; } return (delta/2 - 1); }

  3. Integer Square Root unsigned long sqrt(unsigned long a){ unsigned long square = 1; unsigned long delta = 3; while(square <= a){ square += delta; delta += 2; } return (delta/2 - 1); }

  4. Integer Square Root

  5. State Diagrams unsigned long sqrt(unsigned long a){ unsigned long square = 1; unsigned long delta = 3; while(square <= a){ square += delta; delta += 2; } return (delta/2 - 1); }

  6. A Moore state machine

  7. SQRTctl unsigned long sqrt(unsigned long a){ unsigned long square = 1; unsigned long delta = 3; while(square <= a){ square += delta; delta += 2; } return (delta/2 - 1); }

  8. sqrt

  9. SQRTctl.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity SQRTctrl is Port ( clk : in std_logic; clr : in std_logic; lteflg : in std_logic; strt : in std_logic; ald : out std_logic; sqld : out std_logic; dld : out std_logic; outld : out std_logic; states : out std_logic_vector(1 downto 0)); end SQRTctrl; states(1:0)

  10. A Moore state machine

  11. SQRTctl.vhd (cont.) architecture SQRTctrl of SQRTctrl is type state_type is (start, test, update, done); signal present_state, next_state: state_type; begin sreg: process(clk, clr) begin if clr = '1' then present_state <= start; elsif clk'event and clk = '1' then present_state <= next_state; end if; end process;

  12. A Moore state machine

  13. SQRTctl.vhd (cont.) C1: process(present_state, strt, lteflg) begin case present_state is when start => if strt = '1' then next_state <= test; else next_state <= start; end if; when test => if lteflg = '1' then next_state <= update; else next_state <= done; end if; when update => next_state <= test; when done => next_state <= done; whenothers => null; end case; end process;

  14. A Moore state machine

  15. SQRTctl.vhd (cont.) C2: process(present_state) begin ald <= '0'; sqld <= '0'; dld <= '0'; outld <= '0'; states <= "00"; case present_state is when start => ald <= '1'; states <= "00"; when test => states <= "01"; when update => sqld <= '1'; dld <= '1'; states <= "10"; when done => outld <= '1'; states <= "11"; whenothers => ald <= '0'; sqld <= '0'; dld <= '0'; outld <= '0'; states <= "00"; end case; end process; end SQRTctrl;

  16. sqrt

  17. -- Examples 37 and 38: Integer Square Root library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sqrt is port ( clk : in std_logic; clr : in std_logic; strt : in std_logic; sw : in std_logic_vector(7 downto 0); states : out std_logic_vector(1 downto 0); delta : out std_logic_vector(4 downto 0); root : out std_logic_vector(3 downto 0) ); end sqrt;

  18. architecture sqrt of sqrt is component sqrtctrl port( clk : in std_logic; clr : in std_logic; lteflg : in std_logic; strt : in std_logic; ald : out std_logic; sqld : out std_logic; dld : out std_logic; outld : out std_logic; states : out std_logic_vector(1 downto 0)); end component; states(1:0)

  19. delta(4:0) states(1:0) square(7:0) component sqrtpath port( clk : in std_logic; reset : in std_logic; ald : in std_logic; sqld : in std_logic; dld : in std_logic; outld : in std_logic; sw : in std_logic_vector(7 downto 0); lteflg : out std_logic; root : out std_logic_vector(3 downto 0); square : out std_logic_vector(7 downto 0); delta : out std_logic_vector(4 downto 0)); end component;

  20. delta(4:0) states(1:0) square(7:0) signal lteflg, ald, sqld, dld, outld: std_logic; signal square : std_logic_vector(7 downto 0); begin sqrt1: SQRTctrl port map (clk => clk, clr => clr, lteflg => lteflg, strt => strt, ald => ald, sqld => sqld, dld => dld, states => states, outld => outld); sqrt2: SQRTpath port map ( clk => clk, reset => clr, ald => ald, sqld => sqld, dld => dld, outld => outld, sw => sw, lteflg => lteflg, root => root, square => square, delta => delta); end sqrt;

  21. Top-Level Design

  22. library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_unsigned.all; entity sqrt_top is port( mclk : in STD_LOGIC; sw : in STD_LOGIC_VECTOR(7 downto 0); btn : in STD_LOGIC_VECTOR(3 downto 0); ld : out STD_LOGIC_VECTOR(7 downto 0); a_to_g : out STD_LOGIC_VECTOR(6 downto 0); dp : out STD_LOGIC; an : out STD_LOGIC_VECTOR(3 downto 0) ); end sqrt_top; architecture sqrt_top of sqrt_top is

  23. signal xin: std_logic_vector(15 downto 0); signal p: std_logic_vector(9 downto 0); signal clr, clk, cclk, msel: std_logic; signal clkdiv: std_logic_vector(23 downto 0); signal bin, b: STD_LOGIC_VECTOR (7 downto 0); signal root: STD_LOGIC_VECTOR (3 downto 0); signal states: STD_LOGIC_VECTOR (1 downto 0); signal delta: STD_LOGIC_VECTOR (4 downto 0); constant bus_width8: integer := 8;

  24. begin -- Divide the master clock (50Mhz) down to a lower frequency. process (mclk) begin if mclk = '1' and mclk'Event then clkdiv <= clkdiv + 1; end if; end process; -- clk <= clkdiv(0); -- 25 MHz cclk <= clkdiv(17); -- 190 Hz clr <= btn(3); dp <= '1'; -- decimal points off bin <= "0000" & root; msel <= states(1) and states(0); -- 1 in done state xin(15 downto 10) <= "000000"; xin(9 downto 0) <= p(9 downto 0);

  25. U0: clock_pulse port map (inp => btn(0), cclk => cclk, clr =>clr, outp => clk); U1: sqrt port map ( clk => clk, clr => clr, strt => btn(2), sw => sw, root => root, states => states, delta => delta); U2: mux2g generic map(N => bus_width8) port map (a => sw, b => bin, sel => msel, y => b); u3: binbcd8 port map (b => b, p => p); U4: x7segb port map (x => xin, clr => clr, cclk => cclk, an => an, a_to_g => a_to_g); ld(5) <= btn(3); ld(7 downto 6) <= states; ld(4 downto 0) <= delta; end sqrt_top;

  26. Top-Level Design

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