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A Triple Module Redundancy Scheme for SEU Mitigation of Static Latch-Based FPGAs

A Triple Module Redundancy Scheme for SEU Mitigation of Static Latch-Based FPGAs. Carl Carmichael 1 , Brendan Bridgford 1 , Gary Swift 2 , Matt Napier 3 1 Xilinx Corporation, San Jose CA 2 Jet Propulsion Laboratory, Pasadena CA 3 Sandia National Laboratories, Albuquerque NM.

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Block memories - PowerPoint PPT Presentation

A Triple Module Redundancy Scheme for SEU Mitigation of Static Latch-Based FPGAs