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Uneven Bin Width Digitization and a Timing Calibration Method Using Cascaded PLL

Uneven Bin Width Digitization and a Timing Calibration Method Using Cascaded PLL. Wu, Jinyuan Fermilab May. 2014. Introduction. Digitization with uneven bins is needed in FPGA based TDC . The differential nonlinearity is acceptable in many cases.

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Uneven Bin Width Digitization and a Timing Calibration Method Using Cascaded PLL