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HIGH-SPEED VLSI TESTING WITH SLOW TEST EQUIPMENT

HIGH-SPEED VLSI TESTING WITH SLOW TEST EQUIPMENT. Vishwani D. Agrawal Agere Systems Processor Architectures and Compilers Research Murray Hill, NJ 07974 va@agere.com http://cm.bell-labs.com/cm/cs/who/va January 16, 2002. MEANING OF DELAY TEST. V1 V2. Transient region. Inputs.

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Cd4029b test - PowerPoint PPT Presentation

HIGH-SPEED VLSI TESTING WITH SLOW TEST EQUIPMENT