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Chapter 2

Chapter 2. Instruction Level Parallelism. Instruction Level Parallelism (ILP). ILP: Overlap execution of unrelated instructions gcc 17% control transfer 5 instructions + 1 branch Beyond single block to get more instruction level parallelism Loop level parallelism one opportunity, SW and HW

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Vector Processing

Vector Processing. Review. Speculation: Out-of-order execution, In-order commit (reorder buffer+rename registers)=>precise exceptions Branch Prediction Branch History Table: 2 bits for loop accuracy Recently executed branches correlated with next branch?

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731 views • 42 slides

Computer Architecture Principles Dr. Mike Frank

Computer Architecture Principles Dr. Mike Frank. CDA 5155 Summer 2003 Module #18 Scheduling: Basic Static Scheduling & Loop Unrolling, Intro. To Dyn. Sched. Scheduling, Part I. Basic Scheduling Concepts Loop Unrolling. Basic Pipeline Scheduling.

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Chapter 2

Vector Processing

Computer Architecture Principles Dr. Mike Frank