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N2 m2 1 mpyhu - PowerPoint PPT Presentation

IMAGE PROCESSING ON THE TMS320C6X VLIW DSP

IMAGE PROCESSING ON THE TMS320C6X VLIW DSP. Accumulator architecture. Memory-register architecture. Prof. Brian L. Evans in collaboration with Niranjan Damera-Venkata and Magesh Valliappan Embedded Signal Processing Laboratory The University of Texas at Austin Austin, TX 78712-1084

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N2 m2 1 mpyhu - PowerPoint PPT Presentation

IMAGE PROCESSING ON THE TMS320C6X VLIW DSP