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On-Chip Power Network Optimization with Decoupling Capacitors and Controlled-ESRs

On-Chip Power Network Optimization with Decoupling Capacitors and Controlled-ESRs. Wanping Zhang 1,2 , Ling Zhang 2 , Amirali Shayan 2 , Wenjian Yu 3 , Xiang Hu 2 , Zhi Zhu 1 , Ege Engin 4 , Chung-Kuan Cheng 2 1 Qualcomm Inc. 5775 Morehouse Dr., San Diego, U.S.A 2 UC San Diego, U.S.A

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Power network noise - PowerPoint PPT Presentation

On-Chip Power Network Optimization with Decoupling Capacitors and Controlled-ESRs