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A CAD Tool for Scalable Floating Point Adder Design and Generation Using C++/VHDL

A CAD Tool for Scalable Floating Point Adder Design and Generation Using C++/VHDL. By Asim J. Al-Khalili. Overview. Introduction to Floating point Addition Architecture of Single Path FADD Activity Scaling Triple Data Path Floating Point Adder VHDL Modeling Results Implementation.

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Significand length - PowerPoint PPT Presentation

A CAD Tool for Scalable Floating Point Adder Design and Generation Using C++/VHDL