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Threshold design - PowerPoint PPT Presentation

Low-Power Design and Test Gate-Level Power Optimization

Low-Power Design and Test Gate-Level Power Optimization. Hyderabad, July 30-31, 2007 http://www.eng.auburn.edu/~vagrawal/hyd.html. Components of Power. Dynamic Signal transitions Logic activity Glitches Short-circuit Static Leakage. Power of a Transition. i sc. V DD. Dynamic Power

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719 views • 45 slides

Jia Yao and Vishwani D. Agrawal Department of Electrical and Computer Engineering

Dual-Threshold Design of Sub-Threshold Circuits. Jia Yao and Vishwani D. Agrawal Department of Electrical and Computer Engineering Auburn University Auburn, AL 36830, USA. Outline. Motivation and background Single- Vth design Dual- Vth design

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262 views • 14 slides

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Threshold design - PowerPoint PPT Presentation

Low-Power Design and Test Gate-Level Power Optimization

Jia Yao and Vishwani D. Agrawal Department of Electrical and Computer Engineering