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Tiered-Latency DRAM: A Low Latency and A Low Cost DRAM Architecture

Tiered-Latency DRAM: A Low Latency and A Low Cost DRAM Architecture. Donghyuk Lee, Yoongu Kim, Vivek Seshadri , Jamie Liu , Lavanya Subramanian, Onur Mutlu. Executive Summary. Problem : DRAM latency is a critical performance bottleneck

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Tl dram - PowerPoint PPT Presentation

Tiered-Latency DRAM: A Low Latency and A Low Cost DRAM Architecture