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Power and Slew-aware Clock Network Design for Through-Silicon-Via (TSV) based 3D ICs

Power and Slew-aware Clock Network Design for Through-Silicon-Via (TSV) based 3D ICs. Xin Zhao and Sung Kyu Lim School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, Georgia, U.S.A. Reference the slides of this paper in ASPDAC 2010. Outline.

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Tsv upper bound 20 - PowerPoint PPT Presentation

Power and Slew-aware Clock Network Design for Through-Silicon-Via (TSV) based 3D ICs