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Table 7.1 Verilog Operators.

Table 7.1 Verilog Operators. module gatenetwork ( A, B, C, D, X, Y ); input A ; input B ; input C ; input [2:1] D ; output X, Y ; reg Y ; // concurrent assignment statement wire X = A & ~( B | C ) & ( D [1] ^ D [2]);

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Table 7.1 Verilog Operators.