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Simple Testbenches Behavioral Modeling of Combinational Logic

ECE 448 Lecture 4. Simple Testbenches Behavioral Modeling of Combinational Logic. R e quired reading. P. Chu, FPGA Prototyping by VHDL Examples Section 1.4, Testbench Section 3.4, Modeling with a process Section 3.5, Routing circuit with if and case

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Simple Testbenches

ECE 448 Lecture 4. Simple Testbenches. Testbench Defined. Testbench = VHDL entity that applies stimuli (drives the inputs) to the Design Under Test (DUT) and (optionally) verifies expected outputs. The results can be viewed in a waveform window or written to a file.

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Simple Testbenches Behavioral Modeling of Combinational Logic

Simple Testbenches