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전자의료시스템 및 실습 Introduction to DSP

전자의료시스템 및 실습 Introduction to DSP. 구 환 경희대학교 전자정보대학 동서의료공학과. Contents. Introduction - What is a DSP? - Microcontrollers VS DSPs- Technology - Microcontrollers VS DSPs- Architecture - DSP Product Platforms - C2000 Target Markets - C2000 DSP Roadmap - Hardware feature of LF2407

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전자의료시스템 및 실습 Introduction to DSP

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  1. 전자의료시스템 및 실습Introduction to DSP 구 환 경희대학교 전자정보대학 동서의료공학과

  2. Contents • Introduction - What is a DSP? - Microcontrollers VS DSPs- Technology - Microcontrollers VS DSPs- Architecture - DSP Product Platforms - C2000 Target Markets - C2000 DSP Roadmap - Hardware feature of LF2407 - Pin Description - Functional Block diagram

  3. What is a DSP?

  4. Microcontrollers VS DSPs- Technology

  5. Microcontrollers VS DSPs- Architecture

  6. DSP Product Platforms

  7. C2000 Target Markets

  8. C2000 DSP Roadmap

  9. Hardware features of LF2407 • High-Performance Static CMOS Technology • 25-ns Instruction Cycle Time (40 MHz) • 40-MIPS Performance • Low-Power 3.3-V Design • On-Chip Memory • Up to 32K Words x 16 Bits of Flash EEPROM (4 Sectors) • Up to 2.5K Words x 16 Bits of Data/Program RAM • 544 Words of Dual-Access RAM • Up to 2K Words of Single-Access RAM • Boot ROM • SCI/SPI Boot loader • Two Event-Manager (EV) Modules (EVA andEVB), Each Include: • 16-Bit General-Purpose Timers • 16-Bit Pulse-Width Modulation (PWM) Channels

  10. Hardware features of LF2407 • External Memory Interface (LF2407) • 192K Words x 16 Bits of Total Memory : 64K Program, 64K Data, 64K I/O • Watchdog (WD) Timer Module • 10-Bit Analog-to-Digital Converter (ADC) • 500 ns Minimum Conversion Time • Controller Area Network (CAN) Module • Serial Communications Interface (SCI) • 16-Bit Serial Peripheral Interface (SPI) Module • Phase-Locked-Loop (PLL)-Based Clock Generation • Up to 40 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins • Up to Five External Interrupts (Power Drive Protection, Reset, and Two Maskable Interrupts)

  11. Hardware features of LF2407 • Real-Time JTAG-Compliant Scan-Based Emulation, IEEE Standard 1149.1 † (JTAG) • 144-Pin Low-Profile Quad Flat pack ; PGE

  12. Pin Descriptions

  13. Functional Block diagram

  14. Contents • Memory - Harvard Architecture - TMS320C2XX Core Block diagram - TMS320C2XX CPU Architecture - Program memory - Data memory - Memory Map - Peripheral Memory Maps - Internal Memory - Peripherals

  15. Harvard Architecture • Descriptions - 1930년대 말 하버드 대학의 물리학 교수인 Howard Aiken이 고안한 구조 - 프로그램과 데이터를 별도의 메모리에 저장 - 독립된 버스를 이용 - 한 사이클에 Fetch(가져오기)가 가능한 장점

  16. Program Bus Peripherals (Event Mgr) Peripherals (Non-Event Mgr) ALU/Shifters TMS320C2XX Core Block diagram Controller Memory Mapped registers Program Memory A(15-0) D(15-0) Data Bus Multiplier Data Memory

  17. Program Bus 16 Data Bus 16 16 16 32 32 32 32 32 16 MUX 16 16 T(16) MULTIPLIER 16 P(32) Shifter(0-16) Shifter(-6,0,1,4) 32 MUX 32 ALU(32) ACCH(16) ACCL(16) C SFL(0-7) Data Bus TMS320C2XX CPU architecture

  18. Program Bus MUX 16 16 16 16 PC 12-15 16 Address STACK Program ROM/ FLASH (8 * 16) 16 A(15-0) MUX Instruction 16 16 D(15-0) MUX 16 16 16 Data Bus To Data Memory Program memory

  19. Data Bus Program Bus 16 16 16 16 16 9 From Program Memory AR0(16) 16 16 16 3 3 AR1(16) 7 LSB From IR DP(9) AR2(16) 9 AR3(16) 16 3 ARP(3) AR4(16) MUX 16 16 AR5(16) AR6(16) 16 16 AR7(16) MUX ARB(3) ARAU(16) Data/Program RAM 3 MUX Data RAM MUX Data memory

  20. Memory Maps

  21. Peripheral Memory Maps

  22. Internal memory • Dual-access RAM ; 544 words  16 bits • Writes to and reads from the RAM in the same cycle • three block(B1(256) & B2(32) only in data memory space, B0(256) in either data or program memory space) • Single-access RAM(SARAM) ; 2k words × 16 bits • PON & DON bits select SARAM(2k) mapping in program space, data space, or both • Flash EEPROM • partitioned as 4K/12K/12K/4K sectors • Boot ROM • 256 word ROM memory mapped in program space 0000-00FF • enabled if the BOOT_EN pin is low during reset • The boot ROM has a generic bootloader to transfer code through SCI or SPI ports

  23. Peripherals • Tow event-manager modules(EVA, EVB) • Two general-purpose(GP) timers • Three full-compare/PWM units • Three capture units • Two quadrature-encoder pulse(QEP) circuits • Enhanced analog-to-digital(ADC) module • 10-bit ADC core with built-in S/H • Fast conversion time(S/H + Conversion) of 500ns • 16-channel, muxed inputs • Operate as two independent 8-state sequencers or as one large 16-state sequencer(cascaded) • 16 result registers to store • Multiple triggers as sources for the SOC sequence(S/W, EVA, EVB, EXT(ADCSOC pin)

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