Sidewall Image Transfer Technology

1. Sidewall Image Transfer Technology Bobby Schneider

2. Outline • What is Sidewall Image Transfer (SIT)? • Methods A, B, C • What has this been used for? • 0.026 μm² SRAM cell • SIT & the future

3. What is Sidewall Image Transfer? • A processing method • SIT uses optical lithography to obtain sub-resolutionlinewidths! (e.g. 20 nm) • Will be used in next-gen CMOS processing • 22 nm and beyond • Useful for making finFETs

4. Sidewall Image Transfer Method A(The easiest method) • Pattern photoresist (PR) • Deposit a thin conformal film (e.g. 30 nm) • Do a short anisotropic etch • Strip the PR Not flat SIT forms closed loops Microlithography: science and technology  By Kazuaki Suzuki, Bruce W. Smith

5. SIT Design Consideration • Uses two masks • Collar (makes closed loops) • Trim (to define lines) Collar mask Trim mask Result Line-width Pitch

6. Sidewall Image Transfer Method B(Furukawa et al.) Width defined by HF etch duration (e.g. 20 nm) Si Substrate SiO2 Poly-Si Si3N4 Tungsten (W)

7. Sidewall Image Transfer Method B(Furukawa et al.) Width defined by HF etch duration (e.g. 20 nm) Si Substrate SiO2 Poly-Si Si3N4 Tungsten (W)

8. Sidewall Image Transfer Method B(Furukawa et al.) Si Substrate SiO2 Poly-Si Si3N4 Tungsten (W)

9. SIT Method B Result(Furukawa et al.) Small pitch (40 nm pitch possible) Narrow line-width (12 nm width possible) No feet Si Substrate SiO2 Poly-Si Si3N4 Tungsten (W)

10. Sidewall Image Transfer – Method C(Furukawa et al.) Si Substrate SiO2 Poly-Si Si3N4 Photoresist (PR) Germanium (Ge)

11. Sidewall Image Transfer – Method C(Furukawa et al.) Si Substrate SiO2 Poly-Si Si3N4 Photoresist (PR) Germanium (Ge)

12. Sidewall Image Transfer – Method C(Furukawa et al.) Si Substrate SiO2 Poly-Si Si3N4 Photoresist (PR) Germanium (Ge)

13. SIT Method C Result(Furukawa et al.) Small pitch (40 nm pitch possible) Narrow line-width (12 nm width possible) No feet Si Substrate SiO2 Poly-Si Si3N4 Photoresist (PR) Germanium (Ge)

14. How has SIT been used? • “… the smallest FinFET SRAM cell size of 0.063 μm² reported to date using optical lithography.” (Basker et al. 2010)

15. How has SIT been used? (Ctd.)

16. How has SIT been used? (Ctd.) FinFET Performance

17. SIT & The Future • “CMOS Transitions to 22 and 15 nm” • David Lammers, News Editor -- Semiconductor International, 1/1/2010 “Scott Thompson, a former Intel technology manager who now teaches at the University of Florida at Gainesville, believes Intel will adopt a tri-gate structure at some point, while the rest of the industry will shy away from the manufacturing challenges of finFETs.” “I believe most people in the industry would agree that finFET processing is more difficult. Lithography is a huge challenge, though people can overcome that with sidewall image transfer.” -Bruce Doris, manager of advanced device integration at IBM's Albany, N.Y., R&D center

18. Takeaways… • Things to remember: • Sidewall image transfer (SIT) uses optical lithography to achieve very narrow linewidths • 12 nm linewidths achieved, 40 nm pitch • 2 masks: Collar & Trim • Linewidth controlled by etch distance of sidewall • SIT will possibly be used at the 15 nm node of CMOS by Intel

19. Thank you! • That’s all.