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Microprocessors system architectures – IA32 real and virtual-8086 mode

Microprocessors system architectures – IA32 real and virtual-8086 mode. Jakub Yaghob. Compatibility with 16-bit code. Advantages Allows execution of an older code Disadvantages Supports programmer laziness/persistence IA-32 compatibility modes Real mode Virtual- 8086 mode.

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Microprocessors system architectures – IA32 real and virtual-8086 mode

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  1. Microprocessors system architectures – IA32 real and virtual-8086 mode Jakub Yaghob

  2. Compatibility with 16-bit code • Advantages • Allows execution of an older code • Disadvantages • Supports programmer laziness/persistence • IA-32 compatibility modes • Real mode • Virtual-8086 mode

  3. Compatibility mode comparison • Common characteristic • Binary code compatibility with predecessors of IA-32 (8086, 80186, 80286) • Possibility to use some 32-bit features • Real mode • Nearly compatible with 8086 • Starting CPU mode after the RESET • Minimal support from OS • No protection mechanisms • Some important IA-32 features are not available (paging) • Virtual-8086 mode • More differences against 8086 • Part of the protected mode, cannot run without it • Complicated emulation software • Keeps protection • Uses all features of IA-32 (including paging) • Virtualization – more VM86 machines at the same moment • Cannot be entered from the long mode

  4. Real mode • Usage • CPU starting mode • Does not need memory structures, excluding interrupt vector • To this date used for some recovery software • No protection • Features • Real mode address translation • Instruction operands 8- or 16-bit • It is possible to enable 32-bit operation using an instruction prefix • Only 16-bit registers are available • Higher parts only using an instruction prefix • IncludingIPandFLAGS • 16-bit stack • Interrupt vector • Relocatable usingLIDT • All instruction from 80286 and 80287 supported • FS and GS available for IA-32 CPUs

  5. Real mode address translation • Paging • Not supported • Segmentation • Simulates 8086 behavior • No descriptor tables • Segment attributes set to simulate real mode • Based address derive from the visible part • Base = selector * 16 • Segment limit: 216-1 • Segment type: code-writable • Inaccurate 8086 memory model • Address computed in 32 bits • HMA – available memory in the range 100000h-10FFFFh

  6. 16-bit address modes • 16-bit instructions use 16-bit address mode • Offset = [Base] + [Index] + [Displacement] • Base = BX, BP • Index = SI, DI • Use 32-bit address mode with an instruction prefix

  7. Interrupt system • Relocatable vector (IDTR) • Positioned on address 0 • Real mode format: far 16-bit pointers • Interrupt handling • OnlyFLAGS stored • Only IP changes • Stack pointer is onlySP

  8. Virtual-8086 mode • Special task running in the protected mode • Structure of a V86 task • 32-bit TSS • The 8086 program • A V86 monitor • Must run on CPL=0 • Interrupt and exception handling • I/O emulation • Access to the V86 memory • 8086 OS services • 16-bit OS implemented inside the V86 • 16-bit OS implemented using 32-bit OS

  9. Paging in V86 • CPU translates V86 addresses to linear addresses • Linear address can use paging • Advantages • More V86 tasks at a time • Lower 1MB mapped to different physical memory • Emulating 1MB address spaceof the 8086 • Mapping range 100000h-10FFFFh to 0h-0FFFFh • Sharing „ROM“ contents • Memory mapped I/O

  10. Protection within V86 task • Protection is not enforced between the segments • Protection possibilities • Reserving lower 1MB+64K for V86 tasks • V86 cannot generate addresses out of this range • Paging protection • V86 monitor has U/S=0 • Sensitive instructions • IOPL sensitive: CLI, STI, PUSHF, POPF, INT n, IRET • NotIOPL sensitive: IN, OUT, INS, OUTS • IfIOPL<3, then sensitive instructions invoke#GP

  11. Entering V86 mode • CPU runs in V86, ifEFLAGS[VM]=1 • How to set it • Task switch • ReadingEFLAGSfrom TSS before segment registers loading • Return from interrupt handlerIRET • ReadingEFLAGSfrom the stack • VM flag checks • Segment register loading • How to set segment registers caches • Instruction decoding • Instructions not supported by V86 • Instructions sensitive onIOPL • Access rights • V86 always runs with CPL=3

  12. Entering and leaving VM86 – I

  13. Entering and leaving VM86 – II • Task switch • HW interrupt/exception, INT nwhenIOPL=3 • #GPcaused byINTn, IRET, POPF, PUSHF, IN, OUTwhenIOPL<3 • Normal return from protected mode interrupt/exception handler • A return from V86 monitor to redirect an interrupt/exception • Internal redirection ofINTnwhenVME=1, IOPL<3 and the redirection bit is 1

  14. Leaving V86 • Only through an interrupt or exception • HW external interrupt • An exceptioncaused by V86 code • INT n handler • It is possible to directly redirect it back to V86 code • RESET or INIT • HLTinstruction causes#GP

  15. V86 I/O • Protection • Protection of all ports • V86 performs I/O directly (no protection) • Access specific I/O ports • I/O map in the TSS • Access specific I/O memory mapped ports • Paging

  16. Interrupt and exception handling in V86 • All interrupts divided into classes • Class 1 • All exceptions • All HW interrupts including NMI • Class 2 • Maskable HW interrupts whenCR4[VME] =1 • Class 3 • AllINT n • Moreover, handling of classes 2 and 3 depends • IOPL setting • Working withEFLAGS[IF], EFLAGS[VIF], EFLAGS[VIP] • CR4[VME] setting • INT nredirection map in TSS • Virtual interrupt supportEFLAGS[VIF], EFLAGS[VIP]

  17. V86 interrupt handling for class 1 – I • 32-bit interrupt-, trap-, task-gate • Switches to 32-bit and CPL=0 • Saves the state of the segment registers • Clears the segment registersDS, ES, GS, FS • SS:ESP already contains an address for the stack 0 • CS:EIP already contains interrupt handler address • Clearing flagsVM, NT, RF, TFinEFLAGS • Begins execution of interrupt handler • Handling interrupts for V86 • CheckEFLAGS[VM]on the stack • Handling in the protected mode • Invoking V86 monitor • V86 monitor can invoke V86 handler

  18. V86 interrupt handling for class 1 – II

  19. V86 interrupt handling for class 1 – III • Invoking V86 handler from V86 monitor • Use the 8086 interrupt vector to locate V86 handler address • CopyFLAGSandCS:IPfrom the stack 0 to the V86 stack (CPL 3) • Change return address on the stack 0 to the V86 handler • Return using IRETto the V86 • IRETin V86 causes #GPand invokes V86 monitor • CopyFLAGSfrom stack 3 to stack 0 • SetCS:IPon stack 0 to original address of V86 interrupt • Return usingIRETto the V86

  20. V86 interrupt handling for class 2 – I • Maskable V86 interrupt handling using virtual interrupts • Activated byCR4[VME]=1 andIOPL<3 • FlagsVIFandVIPinEFLAGS • Reduces V86 monitor calls when working withIF (PUSHF, POPF, STI, CLI) • Virtualization • CLIandSTIwork withVIF • PUSHFsaves VIF instead ofIF • POPFloads VIFfromIF,IFremains intact • VIPrecords existence of deferred (pending) maskable HW interrupt • VIPchecked by CPU, never set; set by SW

  21. V86 interrupt handling for class 2 – II • Handling maskable HW interrupt • Invoke 32-bit handler • Switch to 32-bit andCPL=0 • Save the V86 state on the stack 0 • Clear the segment registers • Clear theVMflag in EFLAGS • Begin executionof a 32-bit interrupt handler • CheckEFLAGS[VM]on the stack 0 • If the flag is set, call V86 monitor • V86 monitor checksVIFinEFLAGS • IfVIF=0, set theVIPand return to the 32-bit interrupt handler • IfVIF=1, can be handled as class 1 • Return back to V86

  22. V86 interrupt handling for class 2 – III • Deferring interrupt using the flagVIP • Before theVIF is set (POPF, STI),CPU in V86 checks • IfVIP=0, VIFis set and continue • IfVIP=1, #GP exception is invoked • The#GPexception calls V86 monitor • Handle the deferred interrupt • ClearVIPand setVIFinEFLAGSon the stack • Return to V86

  23. V86 interrupt handling for class 3 – I • SW interrupt handling (INT n) • BRM=Bit in Redirection Map in the TSS

  24. V86 interrupt handling for class 3 – II • Redirection map in the TSS • Easier system calls for 16-bit OS • UsingINT nas system calls • INT 21in the MS-DOS

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