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Lecture 5 Control Unit Implementation

Lecture 5 Control Unit Implementation. [1] MAR PC(address), M R(control). Memory Access time. [2] IR MBR(OP-code). [3] Decode instruction Control Signal Generator IR, Address Processor MBR(address).

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Lecture 5 Control Unit Implementation

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  1. Lecture 5Control Unit Implementation CS510 Computer Architectures

  2. [1] MAR PC(address), M R(control) Memory Access time [2] IR MBR(OP-code) [3] Decode instruction Control Signal Generator IR, Address Processor MBR(address) [4] MAR Effective Address, M R/W Memory Access time 6-Step Instruction Cycle … . . . … . . . [5] Data path activation to do operation [6] Decide final PC by this time, go to [1] for the next instruction CS510 Computer Architectures

  3. CPU data path Register File Rd f(Rs1, Rs2) ALU f Simple data move: Rd fI(Rs1, f) Unary operations: Rd fu(Rs1, f) Binary operations: Rd fb(Rs1, Rs2) Micro-Operation Rd: Destination Register Rs1, Rs2: Source Register Micro-operation A Micro-operation generates a finite set of Control Signals at the proper time according to the Machine State and the Control Data to activate the Micro-actions and to update the Control Data Structure. CS510 Computer Architectures

  4. Register File Bus Register Output Register Input Bus ALU f Rd fADD(Rs1, Rs2) Input Bus 1 Rs1 Input Bus 2 Rs2 ADD Rd Output Bus Micro-Action/Micro-Operation Micro-action - An Activation of a part of data path - Selection of a function of the Functional Unit(ALU), Memory ALU: ADD, OR, SHR, etc Memory: R(read), W(write) Micro-operation - A micro-operation can be described in terms of a sequence of micro-actions CS510 Computer Architectures

  5. Rd fADD(Rs1, Rs2) Input Bus 1 Rs1 Input Bus 2 Rs2 Rd Output Bus Input Bus 1 ADD SUB AND Input Bus 2 Rs1 Rs2 Rd ALU . . . Output Bus Activation of Micro-action:An Example ADD CS510 Computer Architectures

  6. Control Point • Control Point: • Hardware locations(gates) to which control signals are applied to achieve the intended set of functions • (a sequence of micro-operations, each of which may also be a sequence of micro-actions) • Register In-Gates • Register Out-Gates • ALU function selection terminals • Memory read/write control signal terminal CS510 Computer Architectures

  7. Load R1 R1 Send R1 … Q . . . R1 Load R2 … D . . . R2 Send R2 … Q . . . R2 Load R3 … D . . . R3 Send R3 … Q . . . R3 Bus … D . . . Register In-Gates Register Out Gates Control Points:Register In-Gate and Out-Gate CS510 Computer Architectures

  8. X Y Cc A C DI C0 Cm Cr Ri Li Ro Lo PS AN AO NS LS RS SE Logic Unit Adder Shifter Z Control Points:ALU Function Selection Points CS510 Computer Architectures

  9. Independent Control Point Example: 32-bit machine with 8 registers ALU has 4 different functions in 32-bit data in parallel Memory has 1 terminal for R/W No. of Control Points: (32 x 8 x 2) + (32 x 4) + 1 = 641 During an instruction execution, usually a group of bits are transferred together as an information Instruction: OP-code, Register Address, Memory Address Floating point numbers: Sign bit, Exponent, Mantissa Others: A number, A character or a character string Each of these groups actually need an identical control signal for each bit within the group -> Each group is associated with one Independent Control Point No. of Independent Control Points (8 x 2) + 4 + 1 = 21 CS510 Computer Architectures

  10. BUS MBR(O) Memory Bus From ALU To ALU 0 . . . 5 . . . 15 0 . . . 5 6 . . . 15 MBR M MBR BUS MBR MBR BUS BUS MBR(O) BUS MBR(A) M MBR ... ... ... ... ... BUS MBR(OP ) M BUSMBR(A) MBR M M MBR MBR BUS M BUS MBR(A) Independent Control Points:Around MBR CS510 Computer Architectures

  11. Micro-Operation Timing • Execution Time of a Micro-Operation - Micro-Cycle Time required to change the information in a set of registers • CPU Clock is the most basic timing signal used for the reliable operation of CPU and CPU Clock Cycle is equal to the Micro-Cycle • Information need to be stored in a register at the end of each micro-cycle, otherwise, information will be lost • Micro-Cycle is determined by the characteristics of FF’s(setup time, hold time, delay) used in registers and the propagation delay of the circuits (ALU) in between the source and destination registers • Micro-Cycle may vary depending on the micro-operation • Signal path, Type of ALU operation CS510 Computer Architectures

  12. Micro-Cycle • Synchronous Fixed: There is only one Micro-Cycle, i.e., all micro-operations’ execution times are assumed to be identical • Synchronous Variable: Certain long micro-operations are allowed to take multiple cycles without causing a state transition, i.e., different micro-cycle lengths are allowed • e.g. Consider the different time requirements by R <- fI(R) and R <- fb(R, R) • Asynchronous: No clock or external mechanism that determines a state transition. Hardly used to control the execution of instructions Micro-Cycle Time It can be broken down into Control Time and Data Path Time • Control Time • Time to decode control data and generate control signals • Data Path Time • Time to transmit control signals and transfer data • Control Time and Data Path Time are partially overlapped in some high performance machines CS510 Computer Architectures

  13. Control Data Machine State Control Rule Control Signal Timing Microprogram or Combinational logic circuit E.g. In state(Machine Cycle) S1, at time(timing state) t1: R1 f(R2, R3) IBus1 R2, IBus2 R3 R1 OBus Generation of Control Signals Clock f S1 Machine Cycle t1 Timing State CS510 Computer Architectures

  14. Operand Store Instruction Fetch Operand Fetch Instruction OP-code Decode Operation Specified Instruction Address Decision Operand Address Compute Operand Address compute Intra-Instruction Sequencing CS510 Computer Architectures

  15. IBus1 IBus2 IR MAR PC Register File Memory ALU MBR +4 OBus Instruction =4 bytes Rd fu(Rs1) Rd fb(Rs1, Rs2) Rd Rs1 Rd Rs1, Rs2 f PC MBR MAR (R, R) Numerical Calculation MBR PC PC (R, IR(addr)) Logical Calculation MAR R R (PC, IR(addr)) Shifts IR +4 R RISC-S Architecture CS510 Computer Architectures

  16. Instruction Operand Operation ADD Rs1, Rs2(S2), Rd Rd Rs1 + Rs2 SUB Rs1, Rs2(S2), Rd Rd Rs1 - Rs2 AND Rs1, Rs2(S2), Rd Rd Rs1 ^ Rs2 OR Rs1, Rs2(S2), Rd Rd Rs1 vRs2 SLL Rs1, Rd Rd logical Shift Left(Rs1) LD S2(Rs1), Rd Rd M[Rs1 + S2] ST S2(Rs1), Rd M[Rs1 + S2] Rd JMP COND, S2(Rs1) (COND=1): PC Rs1 + S2 CALL Rd, S2(Rs1) Rd PC, next PC Rs1 + S2 RET S2(Rs1) PC Rs1 + S2 Instruction Set - RISC-S Representative Instructions ADD Rs1, Rs2, Rd Integer Addition SLL Rs1, Rd Logical Shift Left 1 bit LD S2(Rs1), Rd Load a word JMP COND, S2(Rs1) Conditional Branch CS510 Computer Architectures

  17. ADD SLL LD JMP [1] [2] [3] [4] [5] [6] [7] MAR Rs1 + S2, R; MAR PC, R; MAR PC, R; MAR PC, R; MAR PC, R; PC PC + 4; PC PC + 4; PC PC + 4; PC PC + 4; IR MBR; IR MBR; IR MBR; IR MBR; Rd Rs1 + Rs2; Rd shl Rs1; T/F(test condition), T: PC Ts1 + S2; Rd MBR; Micro-Operations for RISC-S Decode IR; Decode IR; Decode IR; Decode IR; . . . CS510 Computer Architectures

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  21. 2g-address instruction: R f(R, R) When does the operation(f) take place ? Major State - Machine Cycle During a Major State, a memory reference is made, i.e. a Machine Cycle includes a Memory Cycle FETCH: Read an instruction from memory specified by the address in PC, and whatever left to do before making transition to FETCH, EXECUTE, or INDIRECT machine cycle EXECUTE: For the instructions with an operand in memory, read operand to perform operation specified in the instruction, and make a transition to FETCH machine cycle INDIRECT: Read effective address from memory, and make a transition to FETCH or EXECUTE machine cycle - not happen in RISC (1+X)- or (1+g+X)-address instruction: When does the address calculation take place? CS510 Computer Architectures

  22. R-to-R, JMP(direct address) Interrupt RISC-S does not have Indirect Machine Cycle Memory Reference(Indirect address) JMP Indirect FETCH Memory Reference EXECUTE INDIRECT INTERRUPT Machine Cycles CS510 Computer Architectures

  23. Q0 Q1 Major State Q1 Q0 FETCH 0 0 INDIRECT 0 1 EXECUTE 1 0 INTERRUPT1 1 FET←INT INT←FET EXE←FET INT←EXE INT←FET FET←INT FET←FET FET←EXE FET←EXE EXE←FET INT←EXE FET←FET J Q0 J Q1 FET FF0 FF1 K Q0' K Q1' IND Clock EXE INT t3 Machine State Register(Major State Register) CS510 Computer Architectures

  24. CPU Clock Machine Cycle t0 t1 t2 t3 Memory Cycle (Memory Active) Memory Access time (Read Data available) A timing state counter counts from 0 to 3 Timing State Timing State Counter - A counter that advances for each CPU clock pulse - Counter advances in the period of Micro-cycle - Counter resets at the maximum count, i.e., at the beginning of each Machine Cycle CS510 Computer Architectures

  25. MAR MBR, R; PC PC + 4; IR MBR, Decode; MBR MBR(A); MAR MBR, R; PC PC + 4; IR MBR, Decode; MBR PC+MBR(A); MAR MBR, R; PC PC + 4; IR MBR, Decode; MBR MBR(A); MAR MBR, R; PC PC + 4; IR MBR, Decode; MBR AC+MBR(A); MAR MBR, R; - AC AC + MBR; - MAR MBR, R; - AC AC + MBR; - MAR MBR, R; - AC AC + MBR; - Immediate Address PC Relative Address Direct Address Indirect Address ADD #X ADD $X ADD X ADD @X [1]t0 [2]t1 [3]t2 [4] t3 [5] t0 [6] t1 [7] t2 [8] t3 [9] t0 [10] t1 [11] t2 [12] t3 MAR MBR, R; - - - Machine Cycle:Various Addressing Modes in AC Machines FETCH;INDIRECT;EXECUTE Notice that memory cycle is 4 times slower than the micro-cycle(3 micro-cycle Access Time), and that 4 micro-cycle machine cycle is possible with a faster memory. CS510 Computer Architectures

  26. ADD SLL LD JMP t0 MAR PC, R; MAR PC, R; MAR PC, R; MAR PC, R; t1 PC PC + 4; PC PC + 4; PC PC + 4; PC PC + 4; t2 IR MBR, Decode; IR MBR, Decode; IR MBR, Decode; IR MBR, Decode; t3 Rd Rs1 + Rs2, Rd shl Rs1, MAR Rs1 + S2, T/F(test condition), T: PC Rs1 + S2, RI: INTERRUPT, RI: INTERRUPT, RI: INTERRUPT, RI’: FETCH; RI’: FETCH; RI’: FETCH; t0R; t1- t2 Rd MBR; t3RI: INTERRUPT, RI’: FETCH; FETCH; EXECUTE ALU Control Machine Cycle - RISC-S CS510 Computer Architectures

  27. X Y Cc A C DI C0 Cm Cr Ri Li Ro Lo PS AN AO NS LS RS SE Logic Unit Adder Shifter Z ALU Control CS510 Computer Architectures

  28. ICPs C0 Cm A DI Cc Cr AN AO PS NS LS RS SE Add 0 0 1 0 0 0 d 0 0 1 0 0 1 Increment 1 0 1 1 0 0 d 0 0 1 0 0 1 1’s Compl Add 0 1 1 0 0 0 d 0 0 1 0 0 1 2’s Compl Add 1 1 1 0 0 0 d 0 0 1 0 0 1 AND d d 0 d 0 0 1 1 0 1 0 0 1 OR d d 0 d 0 0 0 1 0 1 0 0 1 Compl AC 0 1 1 1 0 0 d 0 0 1 0 0 1 Left Shift 0 d 0 d 0 0 d 0 1 0 1 0 1 Right Shift 0 d 0 d 0 0 d 0 1 0 0 0 1 Pass d d 0 d 0 0 d 0 1 1 0 0 1 Clear AC d d 0 d 0 0 d 0 0 0 0 0 0 Clear C d d 0 d 0 1 d 0 0 0 0 0 0 Compl C d d 0 d 1 0 d 0 0 0 0 0 0 ALU Control Micro-Actions CS510 Computer Architectures

  29. MAR MBR(addr) AC AC’ AC AC + MBR MAR MBR(addr) + IX Bus conflict • R2 SHL(R1) R1 R2 + R3 These are not concurrent micro-operations even if Adder and shifter are independent units. • R2 SHL(R1) R4 R1 + R3 These are concurrent micro-operations if Adder and shifter are independent units. Constraints on Concurrency Micro-operation concurrency • Hardware resource conflict • Register dependency • However, multiple fan-out of registers may be OK CS510 Computer Architectures

  30. Number of Instruction Machine Cycles Instruction and Machine Cycles 1 Stack Computer: Functional AC Computer: Unary Functional, Control not with Indirect Addr GPR Computer: R-R instructions, Control not with Indirect Addr 2 Transfer and Control Instructions not with Indirect Address AC Computer: Functional GPR Computer: R-M Instruction not with Indirect Address 3 Transfer Instruction with Indirect Address AC Computer: Functional with Indirect Address GPR Computer: R-M Instruction with Indirect Address 4 M-M Instruction not with Indirect Address 5 M-M Instruction with 1 Indirect Address 6 M-M Instruction with 2 Indirect Address CS510 Computer Architectures

  31. State Micro-Operations EXE.t2 (XF.LD): Rd MBR; EXE.t1 (XF.LD’): MBR Rd; (FU’.XF’.CT. IO’)^(T): PC f(Rs1, S2), RI: INT, RI’: FET, FET.t0 MAR PC, R; (FU’.XF. CT’.IO’): MAR f(Rs1, S2), EXE, FET.t3 (FU. XF’.CT’.IO’): Rd f(Rs1, Rs2), RI: INT, RI’: FET, FET.t1 PC PC + 4; FET.t2 IR MBR, Decode; Control Rules for RISC-S (FU’.XF’.CT’.IO): -; EXE.t0 (XF.LD): R, (XF.LD’): W; EXE.t3RI: INT, RI’: FET, Instruction Decode; Functional: FU, Transfer: XF(Load: LD, Store: LD’), Control: CT, I/O: IO Interrupt Request; RI CS510 Computer Architectures

  32. OP-code Cond Independent Control Points IR Flag Major State Rs1 SCC Control Data Rs2 S2(imm) Timing State . . . Rd Control Data Control Logic Circuit Control Unit CPU Implementation Of CU- Hardwired Implementation - CS510 Computer Architectures

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  34. Microprogrammed Control Unit CS510 Computer Architectures

  35. Microprogrammed Control Unit In this topic, we will study • Micro-instruction • Data path control and Sequence control information • Vertical micro-instruction and Horizontal micro-instruction • Microprogramming RISC-S • RISC-S Architecture and Instruction Set • Vertical micro-instruction format • Microprogramming with Vertical micro-instruction • Horizontal micro-instruction format • Microprogram control unit • Advantages and Disadvantages of microprogram CS510 Computer Architectures

  36. Micro-instruction IR Flag Status of CPU Control Point Decoder U-program Control Unit CSAR Control Storage Branch Address Microprogrammed Control Unit CPU Control Unit CS510 Computer Architectures

  37. Micro-Instruction • Micro-instruction should contain • Data Path Control information • Information needed to generate control signals required to activate the data path in the CPU to execute intended micro-operation(s) • Representation of the data path control information • Horizontal Micro-instruction - Direct micro-instruction • Vertical Micro-instruction - Encoded micro-instruction • Sequence Control information • A part of information needed to generate the next micro-instruction address • e.g., Branch address • One micro-instruction may contain both information, • Or, Two types of micro-instructions • Data path control micro-instruction • Sequence control micro-instruction CS510 Computer Architectures

  38. 0 1 2 3 n-1 Sequence Control Control Points CPU Horizontal Micro-Instruction Each of the bits in the data path control information is directly connected to an independent control point, i.e., each bit is associated with a micro-action • Data path control information field is very long • Decoder is not needed to generate control signals, decoding delay is absent • Very fast to execute a micro-instruction • Concurrent micro-operation can be specified if there are multiple data paths • However, in an ordinary machine, micro-instruction bit utilization is poor, thus control storage utilization is inefficient • Very high performance machines can only afford to have HM CS510 Computer Architectures

  39. Vertical Micro-Instruction Data path control information is represented by a set of fields, each of which represents a set of micro-actions associated with a similar hardware resources, e.g: INBUS1, OUTBUS, ALU, Registers, Memory, etc • Information in each field is encoded to reduce the micro-instruction length, thus micro-instruction length is short • Decoder is needed for each encoded field • Concurrency is low, but micro-instruction bit utilization is good, thus control storage utilization is efficient • Generation of control signal is slow due to decoding delay • Easy to make symbolic micro-instructions • Most of commercially available machines employ VM CS510 Computer Architectures

  40. . . . Sequence Control ... ... ... ... . . . Sequence Control ... ... ... Encoding Control Information • Direct Encoding • Indirect Encoding CS510 Computer Architectures

  41. INBUS1 R2 • R3 OUTBUS Micro-Action • Micro-action that activates a data path • Selection of a register whose content can be sent to a bus • Selection of a register that stores the information on a bus • Micro-action that makes the selection of ALU function • For 2’complement ADD • A, C0, Cm, DI’, Cc’, Cr’, AO’, NS, SE • Micro-action that activates the memory control • Memory Read(R) and Write(W) control • R(R) or R’(W) CS510 Computer Architectures

  42. INBUS2 INBUS1 IR MAR PC Register File ALU Flag Memory MBR +4 OUTBUS Example - Architecture:RISC-S CS510 Computer Architectures

  43. 0 Rs2 Cond 1 imm13 Op-code SCC Rd Rs1 S2 31 24 23 19 18 13 12 0 0 000000ADD Rs1,Rs2,Rd Rd Rs1 +Rs2 0 000001SUB Rs1,Rs2,Rd Rd Rs1 - Rs2 0 000100AND Rs1,Rs2,Rd Rd Rs1 ^ Rs2 0 000101OR Rs1,Rs2,Rd Rd Rs1 v Rs2 0 001000SLL Rs1,Rd Rd logical shift left Rs1 1 010000LD S2,Rd Rd M[PC+S2] 1 010001ST Rd,S2 M[PC+S2] Rd 0 100000JMP CD,S2 (COND=1):PC←PC+S2 0 100001CALL Rd,S2 Rd PC, next PC←PC+S2 0 100010RET S2 PC←PC+S2 F: Represents the Function of the instruction T: Represents the Type of the instruction Example - Instruction Set: RISC-S OP-code Symbol Operands Operation 000: Functional, 101: Transfer, 010: Sequencing CS510 Computer Architectures

  44. 00 NOP • 01 Not used • 10 W(Memory MBR) • 11 R(MBR Memory) • 00 Disable • 01 Pass • 10 ADD(Rd Rs1 + Rs2) • 11 2’ complement ADD(Rd Rs1-Rs2) Vertical Micro-Instruction for RISC-S: Data Path Control • Memory Control Field(M: 2 bits) • Memory is either Read or Write, or No-operation, i.e. needs to represent 3 kinds • M • Arithmetic Function Control Field(AF: 2 bits) • ADD, 2’ Complement ADD, Pass, Disable - needs to represent 4 kinds • AF CS510 Computer Architectures

  45. LF • 00 Disable • 01 Not used • 10 OR(Rd Rs1 V Rs2) • 11 AND(Rd Rs1 ^ Rs2) • S • 0 Pass • 1 Shift left(Rd SLL(Rs1)) Vertical Micro-Instruction for RISC-S:Data Path Control • Logical Function Control Field(LF: 2 bits) • AND, OR, Disable - needs to represent 3 kinds • Shift Function Control Field(S: 1 bit) • Either shift left or pass the shifter - needs to represent 2 kinds CS510 Computer Architectures

  46. INBUS2 • IN1 • 00 Disable • 01 INBUS1 PC • 10 INBUS1 Rs1 • 11 INBUS1 MBR INBUS1 IR MAR PC Register File ALU Flag Memory MBR +4 OUTBUS • IN2 • 00 Disable • 01 Not used • 10 INBUS2 IR(imm13) • 11 INBUS2 Rs2 Vertical Micro-Instruction for RISC-S:Data Path Control • Input Bus - INBUS1(IN1: 2 bits) • MBR, PC, R(Rs1), Disable - needs to represent 4 kinds • Input Bus - INBUS2(IN2: 2 bits) • R(Rs2), IR[imm13(S2)], IR[Rs2(S2)], Disable - needs to represent 3 kinds CS510 Computer Architectures

  47. 000 Disable • 001 MAR OUTBUS • 010 MBR OUTBUS • 011 PC OUTBUS • 100 IR OUTBUS • 101 Rd OUTBUS • 110,111 Not used INBUS2 INBUS1 IR MAR PC Register File ALU Flag Memory MBR +4 OUTBUS • 0 Disable • 1 PC PC + 4 Vertical Micro-Instruction for RISC-S:Data Path Control • Output Bus - OUTBUS(OUT: 3 bits) • MAR, MBR, PC, IR, R(Rd), Disable - needs to represent 6 kinds OUT • PC Control Field(P: 1 bit) • PC increment, Disable increment - needs to represent 2 kinds • P CS510 Computer Architectures

  48. xx Next address 00 uPC(repeat) 01 uPC + 1 10 uPC + 2 11 uPC + 3 Data Path Control xx Data Path Control Cond Branch Address Data Path Control Cond C-value Branch Address Vertical Micro-Instruction for RISC-S:Sequence Control • Branch set • Branch set with condition codes • Least significant m bits of address are replaced by the m conditions codes • Complete conditional branch • If CC specified by Cond field is equal to the C-value, address specified in the micro-instruction is the branch address CS510 Computer Architectures

  49. FLG 000 Not branching 001 Unconditional branch 010 Conditional branch on CPU flags(COND field in machine instruction) 011 Not used 100 Conditional branch on T flags 101 Conditional branch on F flags 110,111 Not used Data Path control FLG FVAL address 25 3 4 8 Vertical Micro-Instruction for RISC-S:Sequence Control • Conditions in RISC-S • CPU Flags: C, Z, S, O • Machine language instruction OP-code field: T(t0t1t2) and F(f0f1f2f3) • Branch types: FLG(3 bits) • Conditional branch micro-instruction must specify Branch Type(FLG: 3 bits) and Values of the specified Flags(FVAL: 4 bits) • Maximum number of flags to be tested against the values is 4(CPU flags, F flags) CS510 Computer Architectures

  50. 0 1 2 3 4 5 6 7 8 9 10 11 12 14 15 17 18 21 22 31 M P AF LF S IN1 IN2 OUT FLG FVAL Branch Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 0 M P AF LF S IN1 IN2 OUT 0 1 3 4 7 8 15 1 FLG FVAL Branch Address Vertical Micro-Instruction for RISC-S Vertical micro-instruction formats for RISC-S Data path control micro-instruction for RISC-S Sequence control micro-instruction for RISC-S CS510 Computer Architectures

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