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Reading Assignment: Chapter 3 in Logic and Computer Design Fundamentals 4 th Edition by Mano

Lecture #6 EGR 270 – Fundamentals of Computer Engineering. Reading Assignment: Chapter 3 in Logic and Computer Design Fundamentals 4 th Edition by Mano. In Chapters 1-2 we concentrated on analyzing or minimizing given truth tables or logic diagrams.

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Reading Assignment: Chapter 3 in Logic and Computer Design Fundamentals 4 th Edition by Mano

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  1. Lecture #6 EGR 270 – Fundamentals of Computer Engineering Reading Assignment: Chapter 3 in Logic and Computer Design Fundamentals 4th Edition by Mano In Chapters 1-2 we concentrated on analyzing or minimizing given truth tables or logic diagrams. In Chapter 3 we concentrate more on designing logic circuits to accomplish a given task. Chapter 3 introduces a general design procedurethat can be used to design combinational logic circuits. We will also look at commercially-available logic circuits.

  2. Lecture #6 EGR 270 – Fundamentals of Computer Engineering • Design Procedure (for combinational logic circuits) • Specification: Write a specification for the circuit if one is not provided. • Formulation: Derive the truth table or initial Boolean equations that define the required relationships between inputs and outputs. • Optimization: Apply two-level and multiple-level optimization. Use Boolean algebra, Karnaugh maps, or other techniques to optimize the circuit. Draw a logic diagram using AND, OR, and NOT gates or provide a netlist (software). • Technology Mapping: Transform the logic diagram or netlist to a new diagram or netlist using the available implementation technology. Options might include: • Implement with AND-OR-NOT gates • Implement with Exclusive-OR gates and other basic logic gates • Implement with only NANDs or only NORs • Implement using decoders • Implement using multiplexers • Implement using PLDs or FPGAs (programmable devices) • Verification: Verify the correctness of the circuit using methods such as: • Hand analysis • PSPICE simulation • VHDL simulation • Build in lab and test the circuit

  3. Lecture #6 EGR 270 – Fundamentals of Computer Engineering Example: Design a 4-bit prime number indicator where the output P = 1 when the binary value of the input ABCD represents a prime number.

  4. Lecture #6 EGR 270 – Fundamentals of Computer Engineering Example: Design a 4-bit magnitude comparator, where the output M = 1 when the inputs A3A2A1A0 and B3B2B1B0 are equal.

  5. Lecture #6 EGR 270 – Fundamentals of Computer Engineering Example: Design a code converter to convert a BCD code to an Excess-3 code. Treat all invalid inputs as don’t cares.

  6. Lecture #6 EGR 270 – Fundamentals of Computer Engineering BCD-to-7-segment decoder/driver This is a special type of decoder that is used to drive a 7-segment display. There are two types of 7-segment displays using LED’s: 1) common anode (all anodes at +5V) 2) common cathode (all cathodes at ground) If a common-cathode display is used (as shown below) and if the decoder outputs a HIGH on output a, then segment a will be lit. Note that “current-limiting resistors” are required for each segment or else the segment may be destroyed due to excessive current. The 7448 is a commercially available BCD-to-7-segment decoder/driver with active-HIGH outputs so it is intended to drive a common-cathode display.

  7. Lecture #6 EGR 270 – Fundamentals of Computer Engineering Similarly, a common-anode display requires a driver with active-LOW outputs, such as the 7447. • Figure 3-12 below illustrates which segments would typically be lit for each of the BCD inputs. Note that the unused inputs (10-15) could be handled in a variety of ways: • Blank display • Display unique patterns not equal to any of the decimal digits • Treat as don’t cares for simplest circuit.

  8. Lecture #6 EGR 270 – Fundamentals of Computer Engineering Example: Design a BCD-to-7-segment decoder to drive a common anode display with a blank display for all illegal inputs.

  9. Lecture #6 EGR 270 – Fundamentals of Computer Engineering • Technology Mapping • If an initial design is specified using AND, OR, and NOT gates, the design may then • be converted (or mapped) into a new technology. Examples in the text include: • Mapping a design to NAND logic • Mapping a design to NOR logic • Note that NAND and NOR gates are “universal gates”, meaning that they can be used • to form any other type of basic logic gates. Figure 3-14 on the following page • illustrates the mapping of other gates into NAND and NOR gates. • Show how to form other logic gates using NANDs:

  10. Lecture #6 EGR 270 – Fundamentals of Computer Engineering Figure 3-6: Mapping of AND gates, OR gates, and Inverters to NAND gates, NOR gates, and Inverters.

  11. Lecture #6 EGR 270 – Fundamentals of Computer Engineering • Procedure for converting (mapping) a circuit into NAND or NOR circuits: • Replace each AND and OR gate with the NAND (NOR) gate and inverter equivalent circuits. • Cancel all inverter pairs (back-to-back inverters). • Without changing the logic function, “push” all inverters through branches to represent them as multiple inverters. • Example: Implement the following optimized function with NAND gates and inverters. • F = AB + (AB)’C + (AB)’D’ + E

  12. Lecture #6 EGR 270 – Fundamentals of Computer Engineering Example: Repeat the last example using NOR gates and inverters. F = AB + (AB)’C + (AB)’D’ + E

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