Paradigm Shift to 3D and its Impact on our EcoSystem, Standards and EDA Tools

1. Paradigm Shift to 3D and its Impact on our EcoSystem, Standards and EDA Tools Herb Reiter, eda2asic Consulting Chairman of GSA EDA Interest Group & 3D IC Working Group EDPS, Monterrey, April 8, 2011

2. Agenda • “2D ICs” make continued innovation very expensive • NeedEcoSystemchangestoenablemanyofustocontinue innovating • 3D demands closer cooperation AND additional standards • Data exchange formats & tools interoperability foster cooperation • Complex assembly processes and much higher packing densities demand more rules (… like living in a condo complex vs on a 50 ac ranch…) • 3Dtechnologyoffersnewopportunities for EDA • 3D is a SYSTEM integration technology, not limited to IC design • Opens up a wide range of EDA opportunities: • Engage in multi-level modeling • Make proven 2D tools “3D aware” • Solvecomplexsystem-levelH/W&S/Wplanning,implementation &verificationchallengeswithEDAtools,flows andmethodologies • DFT for economical testing of 3D ICs • Discussion, conclusions, action items

3. Challenges with the proven 2D SoCs • 2+ years development time • Software is ~ ½ of the TTM • NREs of $ 100M and more demand very high volumes to reach breakeven point • RISKs: Design error • Market changes • Competitor moves 1st Synopsys Keynote, @ LSI,Oct6,2010

4. Major Implementation Alternatives Source: eda2asic article in Yole’s 3D Packaging Magazine, Nov 17, 2010

5. 2½+3DCommercializationSchedules 2½D with = this year Dr. Phil Garrou, YOLE http://www.i-micronews.com/lectureArticle.asp?id=6351

6. Semiconductor EcoSystem • Characteristics of our current EcoSystem • ICs, packages and PCBs are designed (almost) in isolation • Monolithic “2D ICs” are hitting economical and technical limits • Severalmodularsolutions(PoP, PiP, SiP,… )areproductionproven • New 2½D* and 3D configurations are emerging as alternativesto integrate ICs and entire systems (*: 2½D = interposer-based) • What do most of our end customers want ? • Lower cost, smarter,faster,smaller systemswithlongerbatterylife • Followinglatesttrendsquickly(shortertime-to-marketin design&manuf.) • How can we meet these requirements ? • Architectfor3Dimplementations(utilizewideI/O,A&D,MEMS,passives) • Higher level of integration allows reduced power and increased speed • Lotsofmemory&S/Wtoincreaseuserfriendliness andupdatesystems • IP reuse and modularity to reduce development time and –cost • Add’l standards to simplifycooperation & drive economies of scale • Investments in our design- and manufacturing EcoSystem

7. Cooperation Within the “Food-Chain” Fabless/light vendor: Idea, architecture, targets for COST, Power, Performance, FormFactor, … Complete Product Foundry contributes: “2D” PDK, die COST, TSV models, TCE data, thermal characteristics, … OS Appl. S/W Drivers Software Partner: H/W & S/W co-design needs, memory footprint, performance, power dissipation, … Wafers Materials vendor: COST, Pkg dimension thermal characteristics,… Soft/Hard IP and/or KGD Package, Interposer, Substrate IP Partner contributes: “2D” license & royalties, models of IP blocks. And for 3D: Licensing & KGD COST, die-level models, … OSAT contributes: COST projections for assembly, test, & shipping. Production test requirements, … Packaged 3D stacks EDA Design Tools/Flows EDA can play an essential role in building the 3D EcoSystem!

8. The Case for Standardsin 3D Design SYSTEM Designers SOFTWARE Designers CIRCUIT Designers Interoperability Design tools Design Rules, Libraries, Models Design Files and Test Programs EDA Vendors Modeling tools Standards for technical hand-off criteria & business responsibilities Standards toexpress material characteristics & manufacturing capabilities Manufacturers Fab, Assembly, Test

9. 3D/TSVModeling&DesignSteps From FABs, OSATs and materials suppliers Major 3D design steps to “hand-off” at fabless / fablight silicon vendors Die- & Block-level IP Models 3D System Design and Partitioning “2D” PDK data “3D” PDK and Wafer, TSV, Interposer, Passives & Package’s: Electrical, thermal & mechanical characteristics 3D-aware IC Layers Implementation 3D-Layers & Stack Verification for Design “hand-off” To Manuf. Standards for modeling and data exchange formats between companies Interoperability between tools

10. NewEDAOpportunitiesin3DEcoSystem H/W Dev. Tools for: S/W Dev. Tools: CO DESIGN MODELING SystemPlanning&Partitioning Including die-level IP Reuse Operating System . Applications Software . . Drivers . . Field Updates Logical & Physical 3D-aware Implementation of new design portion(s) Verification of new design portion(s) and entire system. Test program development Hand-off to manufacturing

11. EDA Opportunities in 3D Design • Modeling tools/flows to expand 2D PDKs to “3D PDKs” • Capture electrical-, thermal-, magnetic-, mechanical characteristics,… • Modify proven 2D tools to make them “3D aware” • PI, SI, noise, temp analysis, TSV strain, P& R ?,… • Create tools for 3D specific new challenges • 3D DFT, die+stack+I/P+passives+pkg co-design, warpage, magnetics,… • Create system-level H/W planning and partitioning tools • “Pathfinding” for lowest cost, lowest power, smallest formfactor,… • Create system-level hardware and software co-design tools • System partitioning in H/W and S/W, emulating, debugging, updating,… -------------------- • Create tools for OS-,appl. S/W-,drivers development & debug • Multi- and many-core, handling of very wide busses, error detection and recovery, managing hardware redundancy (TSVs, memory, logic?, …)

12. A Closer Look at System Design EDA vendors say about system-level tools: • They have to be application specific and utilize a high-level of abstraction to offer significantly higher productivity • Joint development of application-specific tools requires very good cooperation with the actual users at the EDA customers • The number of system designers is much smaller than the number of circuit designers Points above are valid concerns, but keep in mind: • As system complexity and value increase, the need for system-level tools increases beyond C++ to RTL,… large opportunity for EDA ! • Higher abstraction level tools will increase number of system designers • Today’s EDA tools sell per seat for the contract period. Their price is not tiedtothevaluetheycreate  Newbusinessmodelforsystemtools? • System designers who implement large “2D SoCs” can benefits from 3D systemtoolsaswell increases user base and revenues for these tools ! • Systems’ software content is increasing and extends systems’ useful life significantly  Tools for H/W&S/W co-design&S/W development needed!

13. 3D Challenges & Opportunities for EDA • Incremental EDA features and problems associated with migration to 3D • Top-down and very broad-brush perspective • Key challenges are on the System Design Side of things 3D 2D Interface to Manufacturing Physical Design System Design Source: Riko Radojcic, Qualcomm

14. Discussion Topics • When will 2½D cross the chasm? When will 3D …. ? • Which applications will use 2½D first ? // … 3D/TSVs first ? • Are EDA vendors jumping into the 3D drivers seat ? • How are IDMs vs fabless/fablight vendors approaching 3D ? • Would a different EDA biz model increase support for 3D ? • Can we jointly define open EDA standards for 3D or do we want to wait for de-facto (= proprietary) standards ? • Whatarebiggeropportunities(vs3D)togrowEDArevenues? • NEXT technologies: 3DmonolithicICsandCarbonNanotubes

15. Thank You ! Cooperation Standards System-level Business Model herb@eda2asic.com