1 / 52

Chapter One Introduction to Pipelined Processors

Chapter One Introduction to Pipelined Processors. Principle of Designing Pipeline Processors. (Design Problems of Pipeline Processors). Job Sequencing and Collision Prevention. State Diagram. Suppose a pipeline is initially empty and make an initiation at t = 0.

shanon
Download Presentation

Chapter One Introduction to Pipelined Processors

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Chapter One Introduction to Pipelined Processors

  2. Principle of Designing Pipeline Processors (Design Problems of Pipeline Processors)

  3. Job Sequencing and Collision Prevention

  4. State Diagram • Suppose a pipeline is initially empty and make an initiation at t = 0. • Now we need to check whether an initiation possible at t = i for i > 0. • bi is used to note possibility of initiation • bi = 1  initiation not possible • bi = 0  initiation possible

  5. State Diagram bi 1 0 1 0 0 1

  6. State Diagram • The above binary representation (binary vector) is called collision vector(CV) • The collision vector obtained after making first initiation is called initial collision vector(ICV) ICVA = (101001) • The graphical representation of states (CVs) that a pipeline can reach and the relation is given by state diagram

  7. State Diagram • States (CVs) are denoted by nodes • The node representing CVt-1 is connected to CVt by a directed graph from CVt-1 to CVt and similarly for CVt* with a * on arc

  8. Procedure to draw state diagram • Start with ICV • For each unprocessed state, say CVt-1, do as follows: • Find CVt from CVt-1 by the following steps • Left shift CVt-1 by 1 bit • Drop the leftmost bit • Append the bit 0 at the right-hand end

  9. Procedure to draw state diagram • If the 0th bit of CVt is 0, then obtain CV* by logically ORing CVt with ICV. • Make a new node for CVt and join with CVt-1 with an arc if the state CVt does not already exist. • If CV* exists, repeat step (c), but mark the arc with a *.

  10. State Diagram 1 0 1 0 0 1

  11. State Diagram 1 0 1 0 0 1 Left Shift 0 1 0 0 1 0

  12. State Diagram 1 0 1 0 0 1 Zero  CV* exists 01 0 0 1 0

  13. State Diagram 1 0 1 0 0 1 * 0 1 0 0 1 0 1 1 1 0 1 1 ICV – 101001 OR CVi – 010010 CV* 111011

  14. State Diagram 1 0 1 0 0 1 * Left Shift 0 1 0 0 1 0 1 1 1 0 1 1 Left Shift No CV* No CV* 1 0 0 1 0 0 1 1 0 1 1 0

  15. State Diagram 1 0 1 0 0 1 * 0 1 0 0 1 0 1 1 1 0 1 1 Left Shift * 1 0 0 1 0 0 1 1 0 1 1 0 Left Shift Zero  CV* exists No CV* 1 0 1 1 0 0 0 0 1 0 0 0 ICV – 101001 OR CVi – 001000 CV* 101001

  16. State Diagram 1 0 1 0 0 1 * 0 1 0 0 1 0 1 1 1 0 1 1 * 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 Zero  CV* exists * 0 1 0 0 0 0 1 1 1 0 0 1 ICV – 101001 CVi – 010000 CV* 111001

  17. 1 0 1 0 0 1 * * 0 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 Zero  CV* exists 0 0 1 0 0 0 * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 ICV – 101001 CVi – 011000 CV* 111001

  18. 1 0 1 0 0 1 * * 0 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 No CV*

  19. 1 0 1 0 0 1 * * 0 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 No CV*

  20. 1 0 1 0 0 1 * * 0 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  21. 1 0 1 0 0 1 * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  22. 1 0 1 0 0 1 * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  23. 1 0 1 0 0 1 * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  24. State Diagram • From the above diagram, closed loops can be identified as latency cycles. • To find the latency corresponding to a loop, start with any initial * count the number of states before we encounter another * and reach back to initial *.

  25. 1 0 1 0 0 1 Latency = (3) * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  26. 1 0 1 0 0 1 Latency = (1,3,3) * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  27. 1 0 1 0 0 1 Latency = (4,3) * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  28. 1 0 1 0 0 1 Latency = (1,6) * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  29. 1 0 1 0 0 1 Latency = (1,7) * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  30. 1 0 1 0 0 1 Latency = (4) * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  31. 1 0 1 0 0 1 Latency = (6) * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  32. 1 0 1 0 0 1 Latency = (7) * 0 1 0 0 1 0 1 1 1 0 1 1 * 10 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 * * 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 0 * 1 0 0 0 0 0 * 0 0 0 0 0 0

  33. State Diagram • The state with all zeros has a self-loop which corresponds to empty pipeline and it is possible to wait for indefinite number of latency cycles of the form (1,8), (1,9),(1,10) etc. • Simple Cycle: latency cycle in which each state is encountered only once. • Complex Cycle: consists of more than one simple cycle in it. • It is enough to look for simple cycles

  34. State Diagram • In the above example, the cycle that offers MAL is (1, 3, 3) (MAL = (1+3+3)/3 = 2.33) • Thus we have, • A cycle arrived so is called greedy cycle, which minimize latency between successive initiation

  35. Modified State Diagram • The state diagram becomes cumbersome for longer ICVs. • In modified state diagrams, we represent only states obtained of initiations.

  36. Modified State Diagram • The procedure is as follows: • Start with the ICV • For each unprocessed state, For each bit i in the CVi which is 0, do the following: • Shift CVi left by i bits • Drop i leftmost bits

  37. Modified State Diagram • Append zeros to right • Logically OR with ICV • If step(d) results in a new state then form a new node for this state and join it with node of CVi by an arc with a marking i. Join this new node with node of ICV with an arc having the marking ≥ d (length of ICV)

  38. Modified State Diagram 1 0 1 0 0 1

  39. Modified State Diagram 1 0 1 0 0 1 i =1 ICV – 101001 OR CVi – 010010 CV* 111011 1 1 1 0 1 1 1

  40. Modified State Diagram 1 0 1 0 0 1 ≥6 1 1 1 0 1 1 1

  41. Modified State Diagram 1 0 1 0 0 1 i = 3 ≥6 1 1 1 0 1 1 1 ICV – 101001 OR CVi – 001000 CV* 101001

  42. Modified State Diagram 3 1 0 1 0 0 1 i = 3 ≥6 1 1 1 0 1 1 1

  43. Modified State Diagram 3 1 0 1 0 0 1 i = 4 ≥6 1 1 1 0 1 1 1 ICV – 101001 OR CVi – 010000 CV* 111001

  44. Modified State Diagram 3 1 0 1 0 0 1 ≥6 4 1 1 1 0 1 1 1 1 1 1 0 0 1 ICV – 101001 OR CVi – 010000 CV* 111001

  45. Modified State Diagram 3 1 0 1 0 0 1 ≥6 ≥6 4 1 1 1 0 1 1 1 1 1 1 0 0 1

  46. Modified State Diagram 3 ≥6 1 0 1 0 0 1 ≥6 ≥6 4 1 1 1 0 1 1 1 1 1 1 0 0 1

  47. Modified State Diagram 3 ≥6 1 0 1 0 0 1 ≥6 ≥6 4 1 1 1 0 1 1 1 1 1 1 0 0 1 i = 3 ICV – 101001 OR CVi – 011000 CV* 111001

  48. Modified State Diagram 3 ≥6 1 0 1 0 0 1 ≥6 ≥6 4 1 1 1 0 1 1 1 3 1 1 1 0 0 1

  49. Modified State Diagram 3 ≥6 1 0 1 0 0 1 ≥6 ≥6 4 1 1 1 0 1 1 1 3 1 1 1 0 0 1 i = 3 ICV – 101001 OR CVi – 001000 CV* 101001

  50. Modified State Diagram 3 ≥6 1 0 1 0 0 1 ≥6 ≥6 4 1 1 1 0 1 1 3 1 3 1 1 1 0 0 1

More Related