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CPE 528: Session #7

CPE 528: Session #7. Department of Electrical and Computer Engineering University of Alabama in Huntsville. Outline. Sequential Network Models FFs, Latches, Registers Counters FSMs Files. library ieee; use ieee.std_logic_1164.all;

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CPE 528: Session #7

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  1. CPE 528: Session #7 Department of Electrical and Computer Engineering University of Alabama in Huntsville

  2. Outline • Sequential Network Models • FFs, Latches, Registers • Counters • FSMs • Files UAH-CPE528

  3. library ieee; use ieee.std_logic_1164.all; entity flop is port(C, D : in std_logic; Q : out std_logic); end flop; architecture archi of flop is begin process (C) begin if (C'event and C='1') then Q <= D; end if; end process; end archi; library ieee; use ieee.std_logic_1164.all; entity flop is port(C, D, CLR : in std_logic; Q : out std_logic); end flop; architecture archi of flop is begin process (C, CLR) begin if (CLR = '1')then Q <= '0'; elsif (C'event and C='0')then Q <= D; end if; end process; end archi; D-FFs UAH-CPE528

  4. library ieee; use ieee.std_logic_1164.all;entity latch is port(G, D : in std_logic; Q : out std_logic); end latch; architecture archi of latch is begin process (G, D) begin if (G='1') then Q <= D; end if; end process; end archi; library ieee;use ieee.std_logic_1164.all;entity latch is port(G, D, CLR : in std_logic; Q : out std_logic); end latch; architecture archi of latch is begin process (CLR, D, G) begin if (CLR='1') then Q <= '0'; elsif (G='1') then Q <= D; end if; end process; end archi; Latches UAH-CPE528

  5. library ieee; use ieee.std_logic_1164.all; entity flop is port(C, CE, PRE : in std_logic; D : in std_logic_vector (3 downto 0); Q : out std_logic_vector (3 downto 0)); end flop; architecture archi of flop is begin process (C, PRE) begin if (PRE='1') then Q <= "1111"; elsif (C'event and C='1')then if (CE='1') then Q <= D; end if; end if; end process; end archi; 4-bit Register UAH-CPE528

  6. library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter is port(C, CLR : in std_logic; Q : out std_logic_vector(3 downto 0));end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C, CLR) begin if (CLR='1') then tmp <= "0000"; elsif (C'event and C='1') then tmp <= tmp + 1; end if; end process; Q <= tmp; end archi; 4-bit Unsigned Up Counter UAH-CPE528

  7. General Form of a Sequential Network W Combinational Combinational Z Flip-flops circuit circuit Q Clock UAH-CPE528

  8. An Example Reset w = 1 ¤ ¤ A z = 0 B z = 0 w = 0 w = 0 w = 1 w = 0 ¤ C z = 1 w = 1 UAH-CPE528

  9. USE ieee.std_logic_1164.all ; ENTITY simple IS PORT (Clock, Resetn, w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END simple ; ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y : State_type ; BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN -- cont’d ... VHDL Model UAH-CPE528

  10. CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; WHEN C => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; END CASE ; END IF ; END PROCESS ; z <= '1' WHEN y = C ELSE '0' ; END Behavior ; VHDL Model (cont’d) UAH-CPE528

  11. -- same as before ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y_present, y_next : State_type ; BEGIN PROCESS ( w, y_present ) BEGIN CASE y IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; WHEN B => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; WHEN C => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; END CASE ; END PROCESS ; VHDL Model – Alternative Style UAH-CPE528

  12. PROCESS ( Clock, Resetn ) BEGIN IF Resetn = '0' THEN y_present <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN y_present <= y_next ; ENDIF; END PROCESS ; z <= ‘1’ WHEN y_present = C ELSE ‘0’; END Behavior ; VHDL Model – Alternative Style (cont’d) UAH-CPE528

  13. Files • File input/output in VHDL • Used in test benches • Source of test data • Storage for test results • VHDL provides a standard TEXTIO package • read/write lines of text UAH-CPE528

  14. Files UAH-CPE528

  15. Standard TEXTIO Package • Contains declarations and procedures for working with files composed of lines of text • Defines a file type named text: type text is file of string; • Contains procedures for reading lines of text from a file of type text and for writing lines of text to a file UAH-CPE528

  16. Reading TEXTIO file • Readline reads a line of text and places it in a buffer with an associated pointer • Pointer to the buffer must be of type line, which is declared in the textio package as: • type line is access string; • When a variable of type line is declared, it creates a pointer to a string • Code variable buff: line; ... readline (test_data, buff); • reads a line of text from test_data and places it in a buffer which is pointed to by buff UAH-CPE528

  17. Extracting Data from the Line Buffer • To extract data from the line buffer, call a read procedure one or more times • For example, if bv4 is a bit_vector of length four, the call read(buff, bv4) • extracts a 4-bit vector from the buffer, sets bv4 equal to this vector, and adjusts the pointer buff to point to the next character in the buffer. Another call to read will then extract the next data object from the line buffer. UAH-CPE528

  18. Extracting Data from the Line Buffer (cont’d) • TEXTIO provides overloaded read procedures to read data of types bit, bit_vector, boolean, character, integer, real, string, and time from buffer • Read forms read(pointer, value) read(pointer, value, good) • good is boolean that returns TRUE if the read is successful and FALSE if it is not • type and size of value determines which of the read procedures is called • character, strings, and bit_vectors within files of type text are not delimited by quotes UAH-CPE528

  19. Writing to TEXTIO files • Call one or more write procedures to write data to a line buffer and then call writeline to write the line to a file variable buffw : line; variable int1 : integer; variable bv8 : bit_vector(7 downto 0); ... write(buffw, int1, right, 6); --right just., 6 ch. wide write(buffw, bv8, right, 10); writeln(buffw, output_file); • Write parameters: 1) buffer pointer of type line, 2) a value of any acceptable type, 3) justification (left or right), and 4) field width (number of characters) UAH-CPE528

  20. An Example • Procedure to read data from a file and store the data in a memory array • Format of the data in the file • address N commentsbyte1 byte2 ... byteN comments • address – 4 hex digits • N – indicates the number of bytes of code • bytei - 2 hex digits • each byte is separated by one space • the last byte must be followed by a space • anything following the last state will not be read and will be treated as a comment UAH-CPE528

  21. An Example (cont’d) • Code sequence: an example • 12AC 7 (7 hex bytes follow)AE 03 B6 91 C7 00 0C (LDX imm, LDA dir, STA ext)005B 2 (2 bytes follow)01 FC_ • TEXTIO does not include read procedure for hex numbers • we will read each hex value as a string of charactersand then convert the string to an integer • How to implement conversion? • table lookup – constant named lookup is an array of integers indexed by characters in the range ‘0’ to ‘F’ • this range includes the 23 ASCII characters:‘0’, ‘1’, ... ‘9’, ‘:’, ‘;’, ‘<‘, ‘=‘, ‘>’, ‘?’, ‘@’, ‘A’, ... ‘F’ • corresponding values:0, 1, ... 9, -1, -1, -1, -1, -1, -1, -1, 10, 11, 12, 13, 14, 15 UAH-CPE528

  22. VHDL Code to Fill Memory Array UAH-CPE528

  23. VHDL Code to Fill Memory Array (cont’d) UAH-CPE528

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