System-on-Packaging: A Broad Perspective from System Design to Technology Development

1. System-on-Packaging: A Broad Perspective from System Design to Technology Development Li-Rong Zheng Lab. of Electronics and Computer Systems Royal Institute of Technology (KTH) SE-164 40 Kista/Stockholm, Sweden Email: lrzheng@ele.kth.se Johan Liu Div. of Electronics Production Chalmers University of Technology (CTH) 412 96 Göteborg, Sweden E-mail: johan.liu@me.chalmers.se

2. Outline • Background: SoC and SoP • The System Challenges • The Technology Challenges • Cope with the New Challenges • Some Research Results • Conclusion

3. Background

4. 109 108 107 106 105 104 103 102 DRAM Memories 256M 4G f300mm 1G 10G Microprocessors 64M f200mm 6G Hz 3.5GHz 16M f150mm 2.5G Hz 4M Pentium 4 Pentium III f125mm 1M ITRS’99 Pentium II Xeon Celeron Devices per chip 256k Pro 80386 Pentium f100mm 80486 64k 80286 16k 68020 f75mm 4k 32032 6800 8086/8088 1k 8048 8080 Z80 4004 Desk calculator 2.0mm 1.2mm 500nm 250nm 130nm 70nm 8.0mm 5.0mm 3.0mm 1.2mm 800nm 350nm 180nm 100nm 50nm 1970 1974 1978 1982 1986 1990 1994 1998 2002 2006 2010 Years SSI MSI VLSI LSI ULSI GSI The challenge: Moore’s Law and Technology Sacling … the performance of an IC, including the number components on it, doubles every 18-24 months with the same chip price ... - Gordon Moore - 1960

5. Changes of IC in Deep Submicron (DSM) Era 1989 1999 0.8mm CMOS 0.18mm CMOS Technology: 0.8mm 0.18mm 0.07mm # of Metal layers: 2~3 6 8-9 G.W. Aspect ratio (t/w): ~0.8 ~1.8 ~2.7 Wire length(m/chip): ~130 ~1,480 ~10,000 Interconnects Start to Dominates Cost and Performance Interconnect starts to be main design constraints IC

6. System Integration: Near Future Scenario Communication Anywhere; Communication Anytime The future system market will be driven by Personal Communication and Computing

7. Technical Disciplines Mixed Signal IC Signal Processing & Digital ASIC SoC/SoP trade-offs RF/Analog IC TRx architectures AD 90º Baseband processing AD Multi-band Multi-mode Antenna Interface TRx calibration TRx control TRx performanc enhancement DA 90º DA Adaptive front-end design SoC/SoP design methodology Noise coupling/ Interference issues Control signals

8. Signal Processing and Communication ------------------ Functional and Physical ULSI Design ----------------- Computer Engineering and Operating Systems ---------------- Logic Memory Analog/RF System & Architecture System-on-Chip system-on-package Performance (function) Figure-of-Merit = Cost x Time-to-Market System Implementation: SoC and SoP • SoC (System-on-Chip): • A single chip integrated system or system platform, including system hardware (digital, analog/RF) and embedded software/OS • Based on DSM CMOS technology • SoP (System-on-Packaging): • A convergent microsystem integrated on a microboard; also a platform based system, including hardware (digital, analog/RF, MEMS) and embedded software/OS • Based on advanced packaging and assembly technologies; • Overcome formidable integration barriers without compromising individual chip or component technologies

9. The on-going Transition towards SoC and SoP: • Has led to much increased system complexity and higher knowledge/expertise encapsulation • hardware, software, mixed signal • design team, electrical robustness, testability and verification • Has lead to paradigm shifts and hence new challenges both in design method and in technology development. • system architecture, design reuse, implementation

10. The System Challenges

11. System Architecture Gap Today’s system products are dominated by PCs, with well defined interfaces and bus standards The future dominating system market is personal communication and computing, which will require computing platforms that are significantly different from today’s general purpose PCs So, system vendors will have to develop new system architectures or system templates, such that they can immediately upgrade their end products when new technologies are available

12. In the future, even a single chip can not be synchronized! 3.5mm 1 clock y2002 y2005 y2008 y2011 y1999 In the future, a chip will have to be synchronized by different clock domains due to interconnect limitation

13. Circuit switching, static routing, time division multiplexing, control is predetermined Packet switching, dynamic routing BPFT1 BPFR1 RF FDMA/CDMA Interconnects (wireless LAN type NOC/NOP) BPFT2 BPFR2 Optical Interconnects ( ATM type NOP) Interconnects in SOPs: Beyond SIA Roadmap? SoP: It’s Actually about a communication Network on a Package (NoP)! It will be platform-based, emphasizing chip-packgaing co-design.

14. The Design Methodology Crisis A coherent view of system design process is needed System Specification Initial Synthesis Performance Estimation System Partitioning Implementation: Interconnection and Technology Mapping Cost Analysis SoC ?? SoP Resource and Design Library Chip design Software Design Prototyping

15. Design Challenges: I Functional design and validation:Functional design for heterogeneous ASIC´s consisting of multiple Digital Signal Processors(DSP) and RISC coreprocessors, with embedded software integrated on chip memories resulting to much higher design abstraction and specification levels in the design process requiring new description languages, synthesis techniques and validating methods. In addition, HW/SW co-design for such embedded multiprocessor system is a key issue.Mixed signal design and validation is another key issue. IP (or virtual components) based design:Significant improvements of reusability and enhanced reusable macro generation in all phases of the design are required, resulting to more efficient Intellectual Property Right (IP) encapsulation. IP based design will lead to product group specific hardware and software architectural platforms. In addition, IP modules, known as virtual components, can be integrated in SoP like traditional real components with better flexibility.

16. Design Challenges: II Interconnection centric design:Design optimization strategies in deep-submicron, where the cost of an interconnection is much higher (for area, power consumption, speed and cost) than a cost of logic cells or transistors, result in a new design paradigm. New chip and system level synchronization strategies for complex circuits are required in order to obtain high system performance and standardized way to integrate complex IP (intellectual property right blocks or virtual components) to designs. Thus, this will define on-chip and off-chip communication architectures, a necessity for platform thinking and efficient IP usage. New system architectures or templates dominated by interconnects other than today’s PC based system are urgently called for. Physical system integration:Low power design strategies for deep sub-micron design for orders of magnitude reduced power consumption are needed in portable applications requiring new efficient power management techniques as well as emphasis ofco-design of system and implementation aspects. Due to VLSI/ULSI scale integration with deep submicron and mixed signal system integration, the chip-package co-design and proper design partitioning for SoC or SoP and technology selection are mandatory SoC/SoP specific circuit techniques:High performance embedded analog, mixed- signal and digital circuit techniques for an integrated heterogeneous system; concurrent design of integraed passive components and the circuits

17. The Technical Challenges

18. Power Density (W/cm2) 10,000 Sun’s Surface Rocket Nozzle 1,000 Nuclear Reactor 100 Hot Plate 10 8086 4004 Pentium Processors 8008 8085 386 286 486 8080 1 Year ‘70 ‘80 ‘90 ‘00 ‘10 Power Dissipation and Thermal Removal Power density is a crisis if current technology scaling continues in mP

19. CMOS chip package requirement projected in 2008 • For high performance products cooled by forced air, the system size will be completely dominated by the fin (the heat sink size) • For hand hold products without any forced air, thermal are removed by substrate. Thermal resistance of interconnect substrate are critical. • Example: 1mm thick Alumina ~0.66oC/W () and FR4 66oC/W ()

20. IBM S390 Servers Technology: Multi-Chip Module Packaging, 75 metal layers Module Size: 127mm x 127 mm Clock (MHz) On-Chip Off-Chip IBM S390/G5 500 300 IBM S390/G6 637 500 IBM z900 (S390/G7) 1100 < 700? Theoretical limitation of off-chip speed (Katopis, EPEP99): 700MHz. Future on-chip speed is > 3GHz Power: 1400 Watt @1GHz High Density Interconnection Substrate Higher I/O numbers require more system level interconnections f70mm With Flip-Chip Connection

21. Interconnect Requirements in a Network-Based Systems • Globl interconnect demand of a 10 by 10 mP array: • P2P connection: 37.5 km • Muli-drop bus: 1.2-4 km • Network-on-Package (64b): ~0.1km • Translate to the technology for the last case: ~20um track (w+s) and 10 metal layers (35% wiring efficiency) Demanding HDI substrates with a large amount of wiring resource, low thermal mismatch, low cost, easy for processing, and environmentally friend

22. Cope with these New Challenges • KTH: • Single level integration packaging modules for high frequency wireless devices; • Concurrent VLSI and packaging design for high frequency circuits and systems; • Unified electro-thermal simulation in high performance electronics; • Mixed signal design in SoP; • Innovation RF blocks in SoP with MEMS and smart devices. • CTH: • Electrical characterization of SoP integrated substrates and low-cost, high frequency interconnect materials and process; • Thermo-mechanical reliability characterization and modeling of SoP technology using embedded active and passive devices, • Process development for prototype SoP module manufacturing and characterization; • Life cycle assessment of SoP technology

23. Decoupling Capacitor High-Q Inductance Prototype Modules ~GHz off-chip data rate per pin measured Power distribution Signal distribution RF IC Digital IC Digital IC Analog IC Dielectrics (10~20mm) L. -R. Zheng et al, IEEE Trans-AVP, no4. 2001 Research Results: Single Level Integrated Packaging Module Base-Substrate

24. m 40 m m S=5 m, W=5 m, t =2 m BCB m t =2, BCB i 35 t =100,BCB i t =2,SiO 30 i 2 t =100,SiO i 2 25 20 15 10 Quality Factor SiO2 5 0 -5 -10 -15 -20 9 10 11 10 10 10 Frequency (Hz) X. Duo et al: IEEE Norchip 2001 Embedded Passive Components and their Electrical Properties

25. COMSI:Cost-performance analysis of Mixed Signal Implementation Algorithm COMSI: Cost (Isolation _dB, f _Hz) Substrate=[lightly-doped-substrate, heavily-oped-substrate, high-resistivity-substrate, SOI-substrate] For i=1:1:4 Loop1: Change distance and obtain isolation If (isolation>Isolation_dB) then Calculate cost1(i) Exit Elsif (distance >Max_Distance) then Cost1(i)=  Exit End Loop2: Using guard ring than change distance If (isolation>Isolation_dB) then Calculate cost2(i) Exit; Elsif (distance >MaxDistance) then Cost2(i)=  Exit End End Cost= min {Cost1(i), Cost2(i)} (i=1,2,3,4) M. Shen et al: this meeting Chip-Packaging co-design for mixed signal system integration

26. Electrical Characterization of SoP Substrate Top view of an MMIC switch circuit embedded in an LCP substrate Measured and typical frequency-domain performance of the embedded MMIC switch in the insertion loss state. G. Zou et al: 8th Int. Adv. Packag. Materials Symp., 2002,

27. Thermal Mechanical Reliability Characterization and Modeling Concept of system in a package (SoP) Temperature distribution in an LCP substrate (=25s used for SoP solution). Temperature distribution with channel cooling in the substrate used for SoP solution. D. C. Whalley et al, Proc.of APACK 2001. J.M. Zhou et al, EurosimE/2001,

28. Chemical plating of copper for SoP module manufacturing Electroless copper plating on LCP. L. Chen et al: this meeting

29. Life Cycle Assessment of SoP Technology Wafer production environmental impact for GaAs compared with Si in terms of environmental loading unit. M. Kristiansson, project work in the course, CTH, 2002

30. Summary • Future SoP products, dominated by personal communication and computing, will have different system architectures than today’s PC based systems. Future SoP will be more likely communication-network based system platforms. • Many new challenges face SoP, including new system templates, co-design methodology, thermal dissipation, high-density interconnect substrates, low parasitic first-level interconnections, cost and reliability issues. • Preliminary research results on the aspects of SoP at KTH and CTH have been summarized. It has been demonstrated that the technology using low-cost LCP substrate may offer an interesting solution for future low-cost, high volume and high frequency applications.