1 / 9

ARM – Asynchronous RISC Microprocessor

ARM – Asynchronous RISC Microprocessor. הטכניון - מכון טכנולוגי לישראל המעבדה למערכות ספרתיות מהירות

shayla
Download Presentation

ARM – Asynchronous RISC Microprocessor

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ARM – Asynchronous RISC Microprocessor הטכניון - מכון טכנולוגי לישראל המעבדה למערכות ספרתיות מהירות הפקולטה להנדסת חשמל Submitted by: Tziki Oz-Sinay, Ori Lempel Supervised by: Roni Mittleman

  2. General Overview The benefits of asynchronous VLSI circuit design include: • Elimination of clock skew problems • Average case performance • Adaptivity to processing and environmental variations • Lower system power requirement • Reduced noise

  3. Project Description Data Cache Inst Cache SDRAM 32MB SDRAM 32MB Program Code (assembler) Altera APEX 20K RS232 Watch Window (debug) PCI Interface

  4. ARM Architecture • Register Set: The ARM provides 8 16-bit general-purpose data registers • Memory Management: • Separate instruction memory and data memory, each having an address space of up to 64Kbytes. • Both memory spaces are layed out in Little-Endian format.

  5. Instruction Set 4 3 3 6 4 3 9 OpCode Rx Ry OpCode Rx Imm movi Rx, Imm addi Rx, Imm subi Rx, Imm mov Rx, Ry add Rx, Ry sub Rx, Ry or, Rx, Ry and Rx, Ry 4 3 3 6 4 12 OpCode Imm OpCode Rx Ry Imm jump Imm lw Rx, Ry, Imm sw Rx, Ry, Imm bez Rx, Ry, Imm

  6. Out Of Order BranchDecision Op[3:0] ALU0PDst[3:0] Execute Retire Decode Rename Write Back Fetch Instruction Cache PDst[3:0] ALU0Res[15:0] SrcVal1[15:0] ALU1PDst[3:0] PC[15:0] Op[3:0] SrcVal2[15:0] ALU1Res[15:0] Date Cache LDst[3:0] LDst[3:0] Imm[11:0] VInst[15:0] Val15:0] LSrc[3:0] Op[3:0] DataIn[15:0] Imm[11:0] Inst[15:0] PDst[3:0] MemPDst[3:0] PDst[3:0] SrcVal1[15:0] DataOut[15:0] Addr[15:0] SrcVal2[15:0] ReadWrite# Imm[11:0] ARM Pipeline

  7. Out-Of-Order Engine branches non-mem inst mem inst non-branch inst BranchDecision to IFU DATA CACHE ALU0 ALU1 RS0 RS1 Inst from ID ROB RAT RRF In Order Out of Order

  8. Hardware Requirements • Gidel PROC20K card comprising: • Altera APEX 20K FPGA (type EP20K400) • 2*32MB SDRAM • Integrated PCI interface • RS232 port Software Requirements • Altera SignalTap2 embedded logic analyzer • ARM assembler

  9. Timeline • 28/12/03(mid semester report): • Asynchronous simulation of IFU+ID based on Balsa code. • Synthesis of IFU+ID pending arrival of debug software. • Detailed translation of uarch to asynchronous enviornment (handshaking, arbitration protocols). • 4/3/04(final report, first semester): • Asynchronous simulation of a complete data-path flow through the pipeline: mov R0, 1 add R0, 1

More Related