1 / 9

Pipelining: Basic Concepts

Understand the basic concepts of pipelining in parallel processing, including synchronous pipeline and pipeline performance. Learn how to execute code on a MIPS pipelined datapath and incorporate stalls or forwarding to resolve dependencies.

shedlund
Download Presentation

Pipelining: Basic Concepts

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Pipelining: Basic Concepts

  2. 1.1 Basic Concepts Consider a task that can be divided into k subtasks • The k subtasks are executed on k different stages • Each subtask requires one time unit • The total execution time of the task is k time units Pipelining is to overlap the execution • The k stages work in parallel on k different tasks • Tasks enter/leave pipeline at the rate of one task per time unit

  3. 1.2 Synchronous Pipeline • Uses clocked registers between stages • Upon arrival of a clock edge … • All registers hold the results of previous stages simultaneously • The pipeline stages are combinational logic circuits • It is desirable to have balanced stages • Approximately equal delay in all stages • Clock period is determined by the maximum stage delay

  4. 1.3 Pipeline Performance

  5. Pipeline Performance (continue) Introduction Compare Single-Cycle, Multi-Cycle, Versus Pipelined Performance: Example:Single-Cycle, Multi-Cycle, Versus Pipelined performance Consider a 5-stage instruction execution pipeline. The operation time are: 200 ps for Memory 200 ps for ALU 150 ps for Register (read and write) Compare Single-Cycle, Multi-Cycle, Versus Pipelined performance assuming: 20% load, 10% store, 40% ALU ,and 30% branch.

  6. (continue)

  7. (continue)

  8. More Examples Problem ??: (?? marks) Consider executing the following code on the MIPS pipelined datapath: add $t5, $t6, $t8 add $t9, $t5, $t4 lw $t3, 100($t9) sub $t2, $t3, $t4 Using the following diagram for the MIPS pipeline, draw the pipeline execution diagram and show the forwarding paths needed to execute the above code while incorporating any stalls or forwarding to resolve the dependencies.  

  9. More Examples Problem ??: (?? marks) Given the following code sequence: LW$t2, 0($t1) Label1: BEQ$t2, $t0, Label2 # Not Taken once, then Taken LW$t3, 0($t2) BEQ$t3, $t0, Label1 # Taken ADD$t1, $t3, $t1 Label2: SW $t1, 0(St2) Assume that this sequence is executed on a pipelined processor with a 5-stage MIPS pipeline using forwarding and a predict-taken branch prediction method. Draw the pipeline execution diagram for this sequence, assuming that branch instructions are resolved in the EX stage. How many clock cycles are needed to execute this sequence?

More Related