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Quiz Session -1

Quiz Session -1 . Question and Answer CMOS VLSI. How many electrons are present in valence orbit of a silicon. 2. 3. 1. 4. Number of transistors in SSI. 10000-100000. 1000-10000. 100-1000. 10-100. How many valence electrons present in phosphorous. 3. 4. 6. 5.

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Quiz Session -1

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  1. Quiz Session -1 Question and Answer CMOS VLSI

  2. How many electrons are present in valence orbit of a silicon 2 3 1 4

  3. Number of transistors in SSI 10000-100000 1000-10000 100-1000 10-100

  4. How many valence electrons present in phosphorous 3 4 6 5

  5. Photoresit is used for _______ None. Contact cut Covering Masking

  6. MOS transistor is modeled as both a and b voltage controlled voltage source current controlled current source voltage controlled current source

  7. Which metal (impurities) used for to make n region All of the above Aluminium boron phosphorus

  8. Arrange the several layer formations in an order: 1) Metal for contact 2) A thick layer of SiO2 3) A P-type substrate. 4) Poly for gate. 5) After mask thin layer of SiO2 for poly-Si. 6) Paths of n- diffusion. 7) A further layer of SiO2 contact cut. none 2314567 1234567 325671

  9. Arrange masking levels for n-well process steps are • Thinox • N-well mask • Polysilicon mask • Over glass • N+ mask • P+mask • Metal mask • Contact mask G A D C F E H B A B D C F E H G B A D C F E G H B A C F E H G D

  10. Which metal (impurities) used for to make p region Silicon phosphorus Arsenic boron

  11. At present we are at ____ ckt SSI ULSI MSI VLSI

  12. those devices that are normally cutoff with zero gate bias are called as ________ mode transistors. None Both Depletion Enhancement

  13. Photoresit is used for _______ None Cap Covering Masking

  14. Number of transistors in MSI 10-100 10000-100000 2000-3000 100-1000

  15. To manufacture nMOS wafer thickness will be 0.4um 0.4m 0.04mm 0.4mm

  16. Thickox thickness will be 100mm 1mm 100um 1um

  17. Thinox thickness will be 0.1mm 1mm 1um 0.1um

  18. Number of transistors in ULSI 100-2000 10-100 1000-20000 1000000-10000000

  19. At saturation condition Vgs > Vt , Vds > Vgs-Vt Vgs>> Vt , Vds > Vgs-Vt Vgs > Vt , Vds>> Vgs-Vt All of the above

  20. At linear condition Vgs > Vt , Vds= Vgs-Vt Vgs< Vt , Vds < Vgs-Vt Vgs > Vt , Vds< 4.4 Vgs > Vt , Vds< Vgs-Vt

  21. noise margins __________ in CMOS Technology Low High Low compare to BiCMOS High compare to BiCMOS

  22. At cutoff condition 0.4 V > Vt , Vds = 0 V Vgs< Vt , Vds = 0 V Vgs > Vt , Vds = 5 V Vgs > Vt , Vds= 0 V

  23. For going to feature technology which one is alternative to VLSI (silicon) nMOS ECL BiCMOS GaAs

  24. In speed to power scale which technology is good to design the ckt GaAs consumes more power compare to CMOS CMOS processing delay is more compare to GaAs CMOS consumes less power compare to BiCMOS All of the above statements are true

  25. Which scale of technology at present we are 45um 32um 45nm 32nm

  26. Number of transistors in LSI 100-2000 10-100 100-1000 1000-20000

  27. Number of mask steps we are using in p-well design process 6 9 7 8

  28. Whate VLSI stands for Very low scale integrated circuits Very high speed integrated circuits Very large scale integration circuits Very large scale integrated circuits

  29. MOS device is a ____ terminal device 5 2 3 4

  30. switching speed ______in BiCMOS High compare to nMOS High compare to CMOS High Low

  31. _____power dissipationin BiCMOS Low High Low compare to CMOS High compare to CMOS

  32. Number of transistors in VLSI 10-100 1000-20000 100-2000 20000-1000000

  33. Types of e-beam scanning Non of the above Raster Scanning Vector Scanning Both (A) and (B)

  34. CMOS technology prefer to design All of the above High speed parts I/O blocks Logic blocks

  35. BiCMOS is used to design All of the above Critical High speed parts Logic blocks I/O and driver ckt

  36. ECL is used to design All of the above Logic blocks I/O and driver ckt Critical High speed parts

  37. MOS will saturate when ____ occur Vgs > Vt , Vds > Vgs Vgs > Vt , Vds > Vsb-Vt Vgs< Vt , Vds > Vgs-Vt Pinch off

  38. 5th step in n-MOS fabrication Etching poly-si Forming poly-si Forming SiO2 Etching SiO2

  39. 7th step in n-MOS fabrication Diffussep-impurities to make P+ region Diffusse n-impurities to make N region Diffussep-impurities to make P+ region Diffusse n-impurities to make N+ region

  40. In MOS working stage _____and ____will be shorted Gate , Substrate Drain , Substrate Source , Drain Source , Substrate

  41. The _____different processes are their to design CMOS device 1 4 2 3

  42. packing density __________ in CMOS Technology Low High Low compare to BiCMOS High compare to BiCMOS

  43. output drive current in CMOS Technology Low High High compare to BiCMOS Low compare to BiCMOS

  44. In Twin tub process substrate will be _______type P+ N+ p n

  45. Witch type of mask is used in P-well to design n+ regions All of the above –ve n+ mask +ve p+ mask –ve p+ mask

  46. Witch type of mask is used in P-well to design p+ regions All of the above –ve n+ mask –ve p+ mask +ve p+ mask

  47. packing density in BiCMOS Technology High compare to CMOS Low High Low compare to CMOS

  48. MOS device having Bi-directional capability

  49. BiCMOS is a unidirectional device

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