EMCal project TRU (Trigger Region Unit) status Sept ‘08

1. EMCal projectTRU (Trigger Region Unit)status Sept ‘08 Norbert Novitzky

2. Outline • EmCal • General overview • Trigger • Requirements ( design goals, key parameters ): • Schematics ( tower to CTP ) • Trigger mapping • TRU board • Trigger in TRU • L0 latency • STU board • Hierarchical trigger fro EMCal • Our participation • Status • Tests, what are done • Remaining tasks • Time schedule • Future activities

3. EMCal in ALICE Opt. fibers Back plate Led-scintillator 1/3 super module: 48x8 (384) towers. Tables are showing general information about the EMCal detector in ALICE. Because of the similarities with PHOS detector, some information are compared with the PHOS detector.

4. General overview of trigger (EMCaL) The EMCAL will provide L0 and L1 trigger signals. The L0 must be provided within 800ns to CTP, where it is decided with other detectors. The main calculation for L0 is don in TRU level. The L1 is decided in STU. It is more complicated calculation, but first it is needed to transfer the data from TRUs. This procedure start only when the system receive the L0 from CTP (via RCU boards). Other L0 detectors 2x2 data 135ns 29xTRU 12x FEE TRU STU CTP (central trigger processor) L0 signal 600ns L0 800ns 12x FEE TRU t=0 [collision] 12x FEE TRU L1 calculation L1 6200ns End of data 1915ns Data Start of data 1400ns L0 from CTP 1200ns RCU RCU L0 from CTP 1200ns

5. TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU General overview of trigger (EMCaL) • The L0 is generated in TRU (Trigger Region Unit) • The L1 is generated in STU • (Summary Trigger Unit) This figure shows the path for L0 and L1 trigger signals from super modules to the CTP (central trigger processor) CTP Vo multiplicity LTU TTC Level-0 Level-1-L Level-1-M Level-1-H JET 5 Level-1 global decisions in STU f(nxn) High-speed link Ethernet cable STU High-speed link Ethernet cable 16 x TRU 16 x TRU TRU TRU Max 12 m Max 12 m HLT 1 Super module 192 x FEE 192 x FEE RCU DAQ Level-0 local-decisions in TRU (4x4)>x Fake Altro trigger data

6. 8 24 16 0 15 23 7 31 Trigger mapping for EMCaL In this figure we can follow the signal from towers in super module, through the front-end electronics, TRU module until it reach the STU. 1x STU 32 x TRU 384 x FEE 1 FEE card: 32 APD in 8 towers 8 x analogue OR 2x2 STU Summary Trigger 96 (2x2) TRU Trigger region 8 x 48 towers = 384 8 x 12 (2x2) = 96 signals 1 TRU = Analogue FOR cables from 12 FEE 1 FEE 8 x (2x2) 100 ns 1 FEE 8 x (2x2) 100 ns 1 TRU =12 FEE = 1 SM in z 96 ADC 12 bit @40MHz 1 FEE 8 x (2x2) 100 ns ~5-30cm f FPGA Virtex-5 FPGA Virtex-5 4x4 groups Max ~12m z Towers 8 x (2x2) analogue 48 x 8 towers 2x2 CSP numbering 1 FEE = 32 inputs, 8 output for TRU 1 RCU branch A 1..9 1 RCU branch B 10,11,12 Level-1 JET Level-1 High pT Level-0 RCU 1 RCU partition:

7. TRU board LVDS control High speed link (to STU) Power regulators Prom 10 Test pins LVDS bus GTL bus Inputs from FEE – 112 channels (but only 96 will be in use)

8. Trigger (TRU) • Hierarchy of the trigger in EMCal: • The 2x2 sum of the towers from FEE->TRU (112 channels as input in one TRU) • In TRU we create an other 2x2 sum of input channels, what mean now we have 4x4 sum for towers. Then we apply a digital threshold. (69 groups) • The data from TRUs go to STU. • L0: create an OR from every TRU (quick process) • L1 : more complicated, using every TRU data, but it is done in STU 1 Tower 2x2 2x2 = 1 TRU chan. 4x4 for trigger Requirements

9. 40 MHz CTP Decomposition of L0-latency FEE TRU ADC 600ns 580 ns 305 ns 135 ns 345 ns Bx t=0 640 ns Level-0 Algorithm 40 MHz max. 800 ns Maximum time for calculation 235 ns Convert the incoming signal to a digital signal (12 bit) 170ns Reading the data, analog sum (2x2) STU De-serialize the data 69 parallel processes ~ 5 m = 22 ns ~ 35 m = 154 ns Xilinx Virtex-5 20 MHz NRZ Trigger • Every 4x4 calculation will run in parallel processes in the FPGA. • It creates the 4x4 group and check, if the energy reach a certain threshold or not. Every 4x4 group can have different threshold. • The limit to reach the CTP is 800ns. The table shows, how much time is needed to the sub-processes and how much time is left for the calculation

10. STU (Summary Trigger Unit) 32 TRU inputs T18-B19 T20-B21 T22-B23 T26-B27 T28-B29 T24-B25 T30-B31 T32-B33 T34-B35 T16-B17 T14-B15 T12-B13 T10-B11 T4-B5 T6-B7 T8-B9 T36-B37 T2-B3 4 TRU inputs 4 TRU inputs T38-B39 T0-B1 V0 interface Trigger outputs DDL interface DCS interface L0 in TTCRq T0-B1 = Top is input 0, Bottom is input 1

11. STU • The STU has 40 input (for EMCal we will use 32) of high-speed link. • The board also contain an FPGA (Virtex-5, same what we have on TRU) • For generating the L0 signal it will create an OR from every TRU. If one has an L0 signal, then it will send it to CTP. • After that it will create also a L1 trigger signal : • L1 Gamma (is the same procedure, like in TRU 4x4 regions) • Low pT jets • Medium pT jets • High pT jets Below subregion delimitation, 4x4 fast OR  8x8=64 towers Numbers are the readout order and not the ADC channel number Total: 204 subregions

12. FPGA program (basic) There are two main languages in use: VHDL and Verilog The basic component of the program is the CLOCK. Every calculation, every signal is based on this clock. (in TRU it is a 40MHz clock, or we will use the LHC clock ~40.08 MHz) The next is to match the pinout map with the correct chip pins. Every FPGA has different pinout map (we are using Xilinx Virtex-5 LX110 BGA1153). After that the compilation can find the correct way. If you miss the pin, you will not get anything. The pinouts for our FPGA (what is in use)

13. FPGA program (basic) • The start of the program is definition of the ports. • We need to define the signal, what we will use: • IN or OUT signal • The signal is std_logic (standard logic). We can also define it as a vector State mashine A very useful tool in hardware language. Here as a very simple example is a street-light.

14. Our participation in TRU • The production of 38 TRU boards. (including 2 prototypes) • First test of the TRU prototypes before the full production. (Dong, Jo, Hans, Norbert) • First power up • Start to program the FPGA (also Prom) • Test pattern for ADCs • Test of High speed link and LVDS control (with Olivier) • 2 remaining problem before full production: • GTL bus communication • Actel refreshing (not necessary)

15. Test, what we had done • First power up of the board (Problem 1) • All of the starting problems was solved • The power regulators gave the right values (Problem 2) • Some small changes must be made • Programming the FPGA via Xilinx cable: (Problem 3) • Directly – tested • From the flash (prom): • Serial programming (~15 seconds) • Parallel programming (~2-3 seconds) • The test pins are working fine, the LEDs are also ok. • Fake Altro test • The readout of the trigger data with the GTL bus Conclusion The design of the TRU board is good, there is no need to change it. Ready for full production.

16. Test of ADCs The ADCs do the conversion from analog signal to digital (12 bit) signal. After that the FPGA can handle the data. The ADC is working with 40MHz, it can sample the incoming data every 25ns. After that it provides 12 bit digital signal from data. Sampling points (every 25ns) 40MHz – frame clock It’s the start and end of the data. 240 MHz clock – data clock In every rising and falling edge is one bit

17. Test of ADCs • First the testing of the FPGA features. For testing we can use: • Logic Analyzer (10 test pins = 10 channels) • ChipScope – built-in logic analyzer inside FPGA • First thing to do: test the ADCs(12 bits in 8 channels) • The part of the program initializes all the ADCs. You need to write to register few data to initialize the completely. • After that we setup the test patterns: • Sync: 101010101010 (~240MHz clock) • Deskew: 111111000000 (~40MHz clock) 40MHz clock – frame clock 240MHz clock – data clock ADCs 8 channels = 1 chip Deskew test pattern data

18. TRU-STU test First test with slow control: (2 inputs, 2 outputs links) We had to solve some issues with the correct pins in FPGA. We solved it. As far as I understood, it will be not used in final setup. They want to use the black-plane to operate with the board. • Second test was the high-speed link. • (1 input (40MHz clock from STU, later the LHC clock), 3 output links) • We were sending 450 words in packet, instead of 96. We solved also some last-minute issues with program. 4 inputs on STU were tested, worked properly. For further test more time is needed: • Test all inputs (compilation time increases) • Test with few TRU at once. (synchronization)

19. Short term plan • Actel refresh – it protects the FPGA from SUE (single upset events) • Dong is working on that now • This test will be good to be done, but not necessary. Long term plan • After full test of the prototype, we need to start the full production. Ordering the missing parts, sending it to the companies. • Further test with STU-TRU setup. • Writing the final FPGA code for the trigger (with Jo, and maybe Dong)

20. Orders • Resistors and capacitors: ~1000 CHF • Connectors: ~1000 CHF • Chips: ~2000 CHF • ADCs: • SILICA AVNET (FR): 23'964 CHF delivery: about 16/02/09 • AVNET EMG (CH): 24’311 CHF delivery: about 09/02/09 • DIGI-KEY (US): 33’538 CHF delivery: from stock (to be • checked before ordering) • SPOERLE (CH): 34’730 CHF delivery: within 12 weeks • (about 12/02/09) After the components we need to order the boards (2 are already at Cern), and the mounting. This I don’t know how much will cost.

21. Backup

22. First power up of board (Problem 1) • The power supply values needed (INPUT values): • 4.0V @ 3.3 A • 4.2V @ 3.5 A • 3.3V @ 3.0 A If we are not using the backplane, to turn on the board we need to put a jumper on ST1. At first power up we discovered a capacitor (C126) was mounted inversed and making to short circuit. The silk screen shows the plus sign on the wrong side. To be corrected in the mounting files.

23. Testing the volgates (Problem 2) • On the board there are several voltage regulators: • Digital Power • Q2 – 1.0V output • Q1 – 2.5V output • IC33 – 3.3V output • Q3 – 2.5V output • Reg1 – 2.5V output • ADC powers (must be enable from FPGA): • IC31 – 3.3V output • IC32 – 1.8V output • The Q2 must be corrected: • The TPS74410 is switched to TPS74401 • The R68 and R64 must be switched • The C222 need to be changed to 100pF • The bias pin 6 should be connected to 3.3V • IC32: • Same TPS7701 • R81 and R80 must be switched • The pin 6 should be connected to 3.3V • The C227 need to be changed to 100pF

24. More setup for TRUs (Problem 3) There are several options how to use the TRU. The main switch for programming the FPGA is the SW1: Here the R242 and R241 should be removed. This switch determine how should be the FPGA programmed (Prom – parallel or serial, Actel…) The configuration on silkscreen is not correct for the parallel programming.

25. Programming the FPGA (Problem 3) The R124 must be removed to be able to program the FPGA from PROM or ACTEL. It is an active low signal, should be connected to the ground The R71 must be removed for Actel programming (not yet tried) To program the FPGA from PROM: To disable the clock CLKOUT R18 must be removed. Remove the R22 (C240 is not needed)