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DIGITAL LOGIC

2. DIGITAL LOGIC. LEACH, MALVINO & SAHA. Binary Number System.

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DIGITAL LOGIC

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  1. 2 DIGITAL LOGIC LEACH, MALVINO & SAHA

  2. Binary Number System • The Binary Number System is a system that uses only the digits 0 and 1 as codes. All other digits (2 to 9) are not used. To represent decimal number and letters of the alphabet with the binary code, you have to use different strings of binary digits for each number or letter. • The word bit is the abbreviation for binary digit. When binary number has 4 bit, its sometime called nibble, with 8 bits is known as byte.

  3. Basic Gates Pinout Diagram Timing Diagram The figure shows a pinout diagram of a 7432, a TTL quad 2-input OR gate. After connecting a supply voltage of +5V to pin 14 ans a ground to pin 7, You can connect one or more of OR gates to other TTL device. • OR GATE • AND GATE Output (pin 3) is low only When both the inputs are low. Pinout Diagram Timing Diagram The figure shows a pinout diagram of a 7408, a TTL quad 2-input AND gate. After connecting a supply voltage of +5V to pin 14 ans a ground to pin 7, You can connect one or more of AND gates to other TTL device. Output (pin 3) is high only when both input are high (between C & D, G & H, etc).

  4. Boolean Algebra • NOT Operation Y= (Y equals NOT A) Y=0=1 Y=1=0 • OR Operation Y=A+B Y=A+B=1+0=1 (Where A=1 and B=0) Y=A+B=1+1=1 (Where A=1 and B=1) • AND Operation Y=A.B Y=A.B=0.1=0 (Where A=0 and B=1) Y=A.B=1.1=1 (Where A=1 and B=1)

  5. NOR Gates • NOR Gate Symbol Y=A+B (Y Equals NOT A OR B)

  6. The Basic Gates • The three logic circuits, the inverter, the OR gate and the AND gate, can be used to produce any digital system • The Inverter (NOT Gate) The figure shows the pinout diagram of a 7404 hext inverter. The IC contains six inverter. You can connect any or all inverters to other TTL devices.

  7. NOR Gate The figure Shows inverters on the input lines of an AND gate • Bubbled AND Gate • DE MORGANS First Theorem A+B = A . B The complement of a sum equals the product of the complements

  8. NAND Gate • NAND Gate Symbol Y=A.B (Y Equals NOT A AND B)

  9. Universal logic gates – NOR, NAND • Universality of NOR gate • Figure shows how all other logic gates can be obtained from NOR gates. • Universality of NAND gate • Figure shows how all other logic gates can be obtained from NAND gates. (a) NOT from NOR (b) OR from NOR (c) AND from NOR (a) NOT from NAND (b) AND from NAND (c) OR from NAND

  10. NOR Gate The figure Shows inverters on the input lines of an AND gate • Bubbled OR Gate • DE MORGANS Second Theorem A . B= A +B The complement of a Product equals the sum of the complements.

  11. AND-OR-INVERT Gate • AND-OR-INVERT Gate • Expandable AND-OR-INVERT Gate AND-OR Circuit NAND-NAND Circuit AND-OR-INVERT Circuit The widest AND-OR-INVERT gate available in the 7400 series is 4-wide. The two additional inputs, labeled bubble and arrow allow it for 6 or 8-wide circuit.

  12. Positive and Negative Logic Use of binary 0 for low voltage and a binary 1 for high voltage is called Positive Logic. Use of binary 1 for low and binary 0 for high voltage is called Negative Logic. The following discussion introduces some of the terminology and concepts for both type of logic. • Positive and Negative Gates • Positive True and Positive False • Negative True and Negative False • Equivalent Gates • Assertion-Level Logic • Labeling Signals

  13. INTRODUCTION TO HDL • It is textual description of a digital circuit. • Currently, there are two widely used HDLs – Verilog and VHDL (Very high speed integrated circuit Hardware Description Language). • Advantages • describe a large complex design requiring hundreds of logic gates in a convenient manner, in a smaller space. • use software test-bench to detect functional error, if any and correct it (called simulation). • get hardware implementation details (called synthesis). Hardware Description Language, more popular with its acronym HDL is an answer for that.

  14. Verilog HDL • Describing Input Output • In any digital circuit, we find there are a set of inputs and a set of outputs, often termed as ports. Note that, all keywords are written in bold.

  15. Verilog HDL • Writing Module Body • There are three different models of writing module body in Verilog HDL.We start with structural model by example of two-input OR gate • data flow model and behavioral model are the other two models

  16. Verilog HDL • Preparation Of Test Bench Execution of Verilog code generates following timing diagram. One can see that input AB, given by testor.A and testor.B (testor is module name of the test bench) is taking value 00,01,10,11 as expected and retain them for 20 ns Verilog simulation of 2 input OR gate with 20ns gate delay

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