Naming

1. Naming Bus & File System Principles of Computer System (2012 Fall)

2. naming model

3. Module use of names • Two ways modules uses a named object: • By value • Module gets a copy of the named object • By reference • Module operates directly on the named object • Purpose #1: Sharing and Organization • Most communication happens using names • Purpose #2: Delayed binding to an object • Supports replaceability and indirection

4. Modules and names

5. Naming schemes • Three parts • Name space: Symbols and syntax rules for generating names • Name-mapping algorithm: Maps names to values • Universe of values: All possible of values • Terminology • Binding – A mapping from a name to value • A name that has a mapping is bound • A name mapping algorithm resolves a name

6. Naming model

7. NamingContext • Name lookup typical done in a context • Examples: • Mail cse@sjtu.edu.cn • Dial: 51355355 • “Hey, you!” • Name spaces with only one possible context are called universal name spaces • Example: US social security numbers

8. Determining Context - 1 • Hard code it in the resolver • Examples: Many universal name spaces work this way • Embedded in name itself • cse@sjtu.edu.cn： • Name = “cse” • Context = “sjtu.edu.cn” • /ipads.se.sjtu.edu.cn/courses/cse-g/2012f/README： • Name = “README” • Context = “/ipads.se.sjtu.edu.cn/courses/cse-g/2012f”

9. Determining Context - 2 • Taken from environment (Dynamic) • Unix cmd: “rm foo”: • Name = “foo”, • context is current dir • Read 0x7c911109: • Name = “0x7c911109”, • context is thread’s address space • Many errors in systems due to using wrong context

10. Interpreter naming API • value← RESOLVE(name, context) • Return the mapping of name in the context • status ← BIND(name, value, context) • Establish a name to value mapping in the context • status ← UNBIND(name, context) • Delete name from context • list ← ENUMERATE(context) • Return a list of all bindings • result ← COMPARE(name1, name2) • Check if name1 and name2 are equal

11. Uniqueness • Manynamingsystems are not unique • Names can map to 0, 1, or many values • RESOLVE can return NULL or a list of values • A value may have 0, 1, or many names • Reverse RESOLVE can return NULL or a list • Unique identitynamespace • Never reused – called a Stable Binding • Your SJTU student number • Many billing systems have “Customer #s”

12. Name mapping algorithms • Table lookup • Find name in a table • Examples: Phone book, old /etc/hosts • Context: Specify which table to use • Recursive lookup • Multiple lookup

13. Addresses • Addresses are used as both names and locators • e.g. IP address: 171.64.64.64, 1950s phone number, I/O device address • Highly useful but fragility • Work-around when object moves • Change all references - can be painful • Make it work for both new and old • Have client search if resolve fail • Indirection is frequently the solution • Update indirection map to handle moves • Examples: host names, cell phone numbers, etc.

14. BUS： a hardware layer

15. Booting • 3 Abstractions in Computer • Interpreter • Memory • Communication link • Naming in booting • Linux booting sequence • Bus address • Memory load • Mmap I/O & DMA

16. Keep two questions in mind • What is the memory, the interpreter, and the communication link respectively? • What is the name, the context, the name mapping algorithm?

17. Linux booting: 5 stages Init User app on Disk Kernel Linux on Disk Stage 2 bootloader GRUB/LILO on Disk Stage 1 bootloader GRUB on MBR (Disk) System startup BIOS on Flash

18. 1. BIOS • BIOS’s job • 1st instruction: 0xFFFF0 • POST (Power-On Self Test) • Manage resource: name space • Enumerate bus device • Load boot loader into memory & give control to it • Three abstractions • Interpreter: CPU, BIOS controller, memory controller • Memory: flash memory & RAM • Communication link: system bus

19. 2. Bootloader stage 1 (MBR) • MBR (Master Boot Record) • First 512-byte on the disk (the first block) • Bootloader stage 1’s job • Load stage 2 into memory& give control to it • Three abstractions • I: CPU & DC & MC • M: disk & RAM • C: system bus MBR Bootloader 512-byte Partition Table Magic num

20. 3. Bootloader stage 2 • Bootloader stage 2’s job • List boot menu • Load user-selected kernel into memory& give control to it • Three abstractions • I: CPU & DC & MC • M: disk & RAM • C: system bus

21. 4. Kernel • Kernel’s job • Change CPU to protected mode • Initialize system… • Load init into memory and run it • Three abstractions • I: CPU & DC & MC • M: disk & RAM • C: system bus

22. 5. init • init process • The first user space program, pid=1 • The root & parent of all other processes • init’s job • Run /etc/rc.d/rc.sysinit • Start system processes in /etc/inittab • Start multiple “getty” which waits for console logins • Three abstractions • I: CPU & DC & MC • M: disk & RAM • C: system bus

23. Question • How does CPU find the 1st instruction on BIOS? • Hard wire 0xFFFF0 to PC after reset • What happens during a memory load?

24. Booting sequence • Three Abstractions • Interpreter: CPU, memory controller, disk controller • Memory: BIOS’s flash memory, RAM, disk • Communication link: System bus • Common Patterns • Processor read from memory (LOAD) and interpret • Memory cell naming: bus address • I/O devices transfer data to memory • Disk sector naming: block number • DMA & Memory-mapped I/O

25. Specific Operations • Memory Load/Store • Between CPU and memory • Physical memory address space • I/O Operations • MMIO: map device memory and registers into physical address space • E.g., frame buffer • DMA • Also using physical address Processor load/store PIO/MMIO Memory DMA I/O Device

26. A Hardware Layer: the bus

27. Bus: Hardware Layer • Bus feature • A set of wires: comprising addr, data, control lines that connect to a bus interface on each module • Bus arbitration protocol: decide which module may send or receive a message at any particular time • Bus arbiter (optional): a circuit to choose which modules can use the bus • Broadcast link: every module hears every message • Bus address: identify the intended recipient

28. Split-transaction • Source module requires exclusive use of the bus • Source module places a bus address of the destine module on the bus • Source module signals READY wire to alert the other module • The destine module singles ACKNOWLEDGE wire after copied the data • If synchronized, then READY & ACKNOWLEDGE are not needed, just check the address lines on each clock cycle • Source module releases the bus

29. Memory load example: LOAD 1742, R1 Processor #2 => all bus modules: {1742, READ, 102}

30. Memory load example: LOAD 1742, R1 • Memory1 recognizes the address is within its range • By examining just a few high-order address bits

31. Memory load example: LOAD 1742, R1 • Memory1 acknowledges and processor2 releases the bus • Memory1 performs the internal operation to get the value • value <- READ (1742)

32. Memory load example: LOAD 1742, R1 • Memory1 => all bus modules: {102, value}

33. Memory load example: LOAD 1742, R1 • Processor2 is waiting for this result, just copies the data on the bus to its register R1

34. Memory load example: LOAD 1742, R1 • Processor2 acknowledges and memory1 releases the bus

35. Bus Address • Bus address space (physical address) • Each module has its own bus address range • BIOS is in charge of managing at booting time • 1MB in the past, 4GB today, larger in the future • Basic unit: byte • Each module examines the bus address field • For every message • Ignores those not intended for it • What about sniffering?

36. Simple I/O Device in a Similar Way • Example: Keyboard • When user depresses a key, keyboard SENDs a message to the processor containing the key value • As the processor is not ready, its bus interface: • copies the data into a temporary register, • acknowledges the keyboard, • SENDs an interrupt signal to the processor • The processor handles the interrupt in next cycle • SENDs the value over the bus to memory module • Suitable for slow device, not suitable for disk

37. DMA for Disk Device • DMA (Direct Memory Access) • A processor SENDs a request to a disk controller to READ a block of data • Including the address of a buffer in memory • The disk SENDs the data directly to memory • Incrementing the memory address appropriately

38. DMA for Disk Device • Benefits of DMA • Relieve the CPU’s load to execute other program • Reduce one transfer (original two) • Take better advantage of long message if the bus supports • Amortize the overhead of the bus protocol

39. Memory Mapped I/O • Use LOAD and STORE instructions to address the register and buffer of the I/O modules • Just like access memory • Address is overloaded name with location info • Provide a uniform interface to bus modules • MMU translates virtual addr to physical addr • Physical address is system bus address • I/O modules translate bus address to register address internally

40. Memory Mapped I/O Processor Virtual address MMU Physical address (System bus address) Internally translate to register address Memory Disk Keyboard

41. Volatile Address #include <stdio.h> void main() { inti = 10; int a = i; printf("i= %d\n",a); // Change value of i __asm{ movdwordptr [ebp-4], 20h } int b = i; printf("i= %d\n",b); }      

42. Memory Mapped I/O combined with DMA

43. DMA example • Processor #1 => all bus modules: {121, WRITE, 11742} • Disk acknowledge and write the value 11742 to its control register • Processor #1 => all bus modules: {122, WRITE, 3328} • Processor #1 => all bus modules: {123, WRITE, 256} • Processor #1 => all bus modules: {124, WRITE, 1} Processor 2 Processor 1 101 102 256-511 3072-4095 121-124 BIOS Memory Disk

44. DMA example • Disk => all bus modules: {3328, WRITE, data[11742]} • Memory acknowledge and save data[11742] • Disk => all bus modules: {3329, WRITE, data[11743]} • ... (loop) • Disk => all bus modules: {3583, WRITE, data[11997]} Processor 2 Processor 1 101 102 256-511 3072-4095 121-124 BIOS Memory Disk

45. DMA example • When transferring is finished, disk controller SENDs message to the processor • Just like keyboard controller does when press a key • Processor will enter interrupt handler next cycle • Now the processor knows that the DMA is done Processor 2 Processor 1 101 102 256-511 3072-4095 121-124 BIOS Memory Disk

46. Questions • Why not map the whole disk to memory? • So that the CPU can access a byte on the disk directly by system bus • 1. Too large • 2. Too slow The principle of least astonishment: People are part of the system. The design should match the user’s experience, expectations, and mental models

47. file system: a software layer

48. Outline • UNIX file system • 7 layers in file system (3 + 1 + 3) • FS API implementation • OPEN, READ, WRITE, CLOSE, FSYNC • UNIX shell • Implied context, search path, name discovery • Review of naming model

49. File • File is a high-level version of the memory abstraction • A file has two key properties • It is durable & has a name • The system layer implements files using modules from the hardware layer • Divide-and-conquer strategy • Makes use of several hidden layers of machine-oriented names (addresses), one on another, to implement files • Maps user-friendly names to these files • In UNIX, everything is a file- KISS

50. API of the UNIX file system • OPEN, READ, WRITE, SEEK, CLOSE • FSYNC • STAT, CHMOD, CHOWN • RENAME, LINK, UNLINK, SYMLINK • MKDIR, CHDIR, CHROOT • MOUNT, UNMOUNT